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參數(shù)資料
| 型號： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 27/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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Serial Interface
A serial interface is used to write and read the configuration
registers. The interface is a four wire interface using SCLK,
SEN, SDI, and SDO connections. The serial interface clock
(SCLK) must be less than the main input clock (INCLK) for
INCLK speeds of less than 20MHz, for INCLK speeds greater
than 20MHz SCLK must remain below 20MHz. The main in-
put clock (INCLK) to the LM98640QML must be active during
all Serial Interface commands. The Serial Interface pins are
high impedance while SEN is high, this allows multiple slave
devices to be used with a single master device.
After power-up, the configuration registers must be written
with the baseline values, using the serial interface, to place
the part in a valid state.
Writing to the Serial Registers
To write to the serial registers using the four wire interface,
the timing diagram shown in Figure 16 must be met. First,
SEN is toggled low. At the rising edge of the first clock, the
master should assume control of the SDI pin and begin issu-
ing the write command. The write command is built of a "write"
bit (0), device address bit (0), six bit register address, and
eight bit register value to be written. SDI is clocked into the
LM98640QML at the rising edge of SCLK. The LM98640QML
assumes control of the SDO pin during the first eight clocks
of the cycle. During this period, data is clocked out of the de-
vice at the rising edge of SCLK. The eight bit value clocked
out is the contents of the previously addressed register, re-
gardless if the previous command was a read or a write. When
SEN toggles high, the register is written to, and the
LM98640QML now functions with this new data.
Reading the Serial Registers
To read to the serial registers using the four wire interface,
the timing diagram shown in Figure 17 must be met. Reading
the registers takes two cycles. To start the first cycle, SEN is
toggled low. At the rising edge of the first clock, the master
should assume control of the SDI pin and begin issuing the
read command. The read command is built of a "read" bit (1),
device address bit (0), six bit register address, and eight "don't
care" bits. SDI is clocked into the LM98640QML at the rising
edge of SCLK. SEN is toggled high for a delay of at least
t
SENW (see Figure 18). The second cycle begins when SEN is
toggled low. The LM98640QML assumes control of the SDO
pin during the first eight clocks of the cycle. During this period,
data is clocked out of the device at the rising edge of SCLK.
The eight bit value clocked out is the contents of the previ-
ously addressed register. The next command can be sent on
the SDI pin simultaneously during this second cycle. When
SEN toggles high, the register is not written to, but its contents
are staged to be outputted at the beginning of the next com-
mand.
30064759
FIGURE 16. Four Wire Serial Write
33
www.national.com
LM98640QML
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