參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 47/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
Pin Descriptions
Pin
Name
I/O
Typ
Res
Description
1
VCOM1
O
A
Common mode of ADC reference. Bypass with 0.1F capacitor to VSS33.
2
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
3
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
4
VSS33
P
Analog supply return.
5
VSS33
P
Analog supply return.
6
OS1-
I
A
Analog input signal.
7
OS1+
I
A
Sample/Hold Mode Reference Level. Bypassed with a 0.1F to ground in CDS
mode.
8
VSS33
P
Analog supply return.
9
VCLP
O
A
Programmable Clamp Voltage output. Normally bypassed with a 0.1F
capacitor to VSS33.
10
VSS33
P
Analog supply return.
11
OS2+
I
A
Sample/Hold Mode Reference Level. Bypassed with a 0.1F to ground in CDS
mode.
12
OS2-
I
A
Analog input signal.
13
VSS33
P
Analog supply return.
14
VSS33
P
Analog supply return.
15
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
16
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
17
VCOM2
O
A
Common mode of ADC reference. Bypass with 0.1F capacitor to ground.
18
VREFB2
O
A
Bottom of ADC reference. Bypass with a 0.1F capacitor to ground.
19
VREFT2
O
A
Top of ADC reference. Bypass with a 0.1F capacitor to ground.
20
VSS33
P
Analog supply return.
21
VSS33
P
Analog supply return.
22
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
23
VDD33
P
Analog power supply. Decouple with minimum 0.1F capacitor to VSS33 plane.
24
VSS33
P
Analog supply return.
25
SDO
O
D
Serial Interface Data Output. (Tri-State when SEN is high)
26
SDI
I
D
Serial Interface Data Input. (Tri-State when SEN is high)
27
SCLK
I
D
PD
Serial Interface shift register clock. (Tri-State when SEN is high)
28
SEN
I
D
PU
Active-low chip enable for the Serial Interface.
29
NC
No Connection. Can be connected to VSS18.
30
CLPIN
I
D
Input clamp signal.
31
VSS18
P
Digital supply return.
32
VDD18
P
Digital power supply. Decouple with minimum 0.1F capacitor to VSS18 plane.
33
DTM1
O
D
Digital Timing Monitor. If not used, can be connected to VDD18 through a
10k
resistor.
34
DTM0
O
D
Digital Timing Monitor. If not used, can be connected to VDD18 through a
10k
resistor.
35
VDD18
P
Digital power supply. Decouple with minimum 0.1F capacitor to VSS18 plane.
36
VSS18
P
Digital supply return.
37
TXFRM+
O
D
LVDS Frame+
38
TXFRM-
O
D
LVDS Frame-
39
TXOUT3+
O
D
LVDS Data Out3+
40
TXOUT3-
O
D
LVDS Data Out3-
41
TXOUT2+
O
D
LVDS Data Out2+
42
TXOUT2-
O
D
LVDS Data Out2-
43
TXOUT1+
O
D
LVDS Data Out1+
44
TXOUT1-
O
D
LVDS Data Out1-
www.national.com
6
LM98640QML
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