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參數(shù)資料
| 型號(hào)： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 41/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
11 0110
Test Pattern Step
0000 0000
[7:0]
Test Pattern Step Code. Specifies step size in LSB codes the
pattern is incremented in H Gradient and V Gradient pattern. In
Lattice and Stripe pattern it specifies the code during the lower
step.
11 0111
Test Pattern Channel
Offset
0000 0000
[7:0]
Test Pattern Channel Offset Register.
[7:4]
Not Used.
[3:0]
Test Pattern Channel Offset. This specifies the number of lines
the pattern on Channel 2 is delayed from Channel 1. This offset
is maintained throughout the pattern.
11 1000
Test Pattern Value
0000 0000
[15:8]
Upper 8 bits of Test Pattern Value Register. Specifies the upper
8 bits of the test value code during Fixed Pattern and LVDS test,
initial value during H Gradient & V Gradient pattern, and higher
value in the Lattice and Stripe Pattern.
11 1001
Test Pattern Value
0000 0000
[7:0]
Lower 6 bits of Test Pattern Value Register. Specifies the lower
6 bits of the test code value during Fixed Pattern and LVDS test,
initial value during H Gradient & V Gradient pattern, and higher
value in the Lattice and Stripe Pattern.
11 1100
Digital Configuration
0000 0000
[7:0]
Serial Communication Configuration Register.
[7:1]
Not Used.
[0]
Micro-Wire Automatic Read Disable.
0
Read data is always sent out on SDO during the first 8 SCLK
cycles.
The register is selected by the register address in the
previous cycle. (read or write)
1
Automatic read is disabled.
To read from a register two cycles need to be initiated by
the master, first cycle should be a read with the correct
register address and second can be a dummy read or read
from another address or a write cycle, and the data is sent
first 8 SCLK of the second cycle. After a write command
SDO remains in Tri-State during first 8 SCLK.
www.national.com
46
LM98640QML
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