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參數(shù)資料
| 型號(hào)： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 15/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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CDS Mode
In CDS mode, both the Reference Level and Video Level are
presented to the LM98640QML on the OS
X- pin. The OSX+
pin should be bypassed to ground with a 0.1uF capacitor. The
CLAMP pulse is then used to sample the Reference Level and
the SAMPLE pulse is used to sample the Video Level. The
output code will then be the Reference Level minus the Video
Level, or the difference between the Reference Level and
Video Level. A minimum code represents zero deviation be-
tween the Reference and Video Levels and a maximum code
represents a 2V deviation between the Reference and Video
Levels with CDS and PGA gains of 1x.
To place the LM98640QML in CDS Mode from power up, first
write the baseline configuration to the registers as shown in
the Configuration Registers Section. Then ensure S/H mode
is disabled by clearing bit[7] of the Sample & Hold Register
(0x06), then enable CDS mode by setting bit[0] of the Main
Configuration Register (0x00). Next the CLAMP and SAM-
PLE pulses need to be positioned correctly over the reference
and video levels respectively using the CLAMP/SAMPLE Ad-
just.
CDS Mode Bimodal Offset
In CDS mode, the input sampling amplifier has two physical
paths through which a particular pixel will be sampled. These
two sampling paths are a requirement in the Correlated Dou-
ble Sampling architecture. The sampling of the one pixel will
travel the first path (arbritrarily called an even pixel), and the
sampling of the next pixel will travel the second path (called
an odd pixel). The sampling will continue in an even/odd/
even/odd fashion for all pixels processed in a particular chan-
nel. Due to slight variances in the sampling paths (most
commonly a difference in switched capacitor matching), the
processing of identical pixels through the two different paths
may result in a small offset in ADC output data between the
two paths. To correct this, a simple digital offset can be ap-
plied in post processing to either the even pixel data or the
odd pixel data. To simplify this action, the LM98640QML will
indicate (with the TXFRM signal) whether the pixel traveled
the even path or the odd path. For all "Odd" pixels, the TXFRM
signal is high for three TXCLK periods. For "Even" pixels, the
TXFRM signal is high for two TXCLK periods. In Sample and
Hold Mode there is only one sampling path, therefore there is
no need to indicate an even or odd pixel. As a result, the
TXFRM signal is the same for every pixel in Sample and Hold
mode (i.e. high for three TXCLK periods).
CDS Mode CLAMP/SAMPLE Adjust
In CDS mode, the LM98640QML utilizes two input networks,
alternating between them every pixel, to increase throughput
speeds. Because of this, there are two sets of CLAMP and
SAMPLE pulses in the Register Definitions - Timing Config-
uration, one for even pixels and one for odd. Sample Start and
Sample End Registers (0x22,0x23) along with the Clamp
Start and Clamp End Registers (0x20,0x21) control both the
even and odd CLAMP and SAMPLE pulses. To adjust the
CLAMP and SAMPLE pulses, first send the CLAMP
ODD and
SAMPLE
ODD signals to the DTM pins by writing 10 to bits[4:3]
of the Clock Monitor Register (0x09). This will allow the user
to observe the CLAMP
ODD and SAMPLEODD pulses on pins
DTM0 and DTM1 along with the image sensor output using
an oscilloscope. The CLAMP and SAMPLE pulses will only
be shown for every other pixel because of the even odd ar-
chitecture, but the positions of the even CLAMP and SAMPLE
pulses will be identical to that of the odd CLAMP and SAM-
PLE. Then, using the Clamp Start/End and Sample Start/End
registers, adjust the positions of the CLAMP and SAMPLE
pulses to align them over the Reference and Video Levels of
the input signal. To allow for settling and to reduce noise, the
CLAMP and SAMPLE pulses should be made as wide as
possible and placed near the far edge of their respective input
levels.
The following figure shows some examples of input CCD
waveforms and placement of the CLAMP and SAMPLE po-
sitions for each. Ideally the CCD output would line up directly
with the input clock at the AFE inputs, but due to trace delays
in the system the CCD output is delayed relative to the input
clock. In the Delayed CCD waveform the Sample Start/End
Register values are lower than the Clamp Start/End Register
Values. In this situation the sample pulse is not generated
until the next clock period, which allows it to be correctly
placed in the Video Level of the input signal. Notice that edge
zero of the internal clock does not line up with the rising edge
of the input clock. This is due to internal delays of the clock
signals. The amount of delay can be calculated from operat-
ing frequency using the following formula: t
DCLK = 6.0ns + 3/64
* T
INCLK
www.national.com
22
LM98640QML
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