參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 40/50頁
文件大小： 1688K
代理商： LM98640W-MPR
Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
10 1000
DLL Configuration
0000 1111
[7:0]
DLL Configuration Register
[7:1]
Reserved
[0]
DLL Reset. (Self Clearing)
Register Definitions - Digital Configuration
Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
11 0000
Test Pattern Start
0000 0000
[15:8]
Upper 8 bits of the Test Pattern start value. Specifies the number
of pixels after the leading edge of CLPIN to the Valid Pixel region.
11 0001
Test Pattern Start
0000 0000
[7:0]
Lower 8 bits of the Test Pattern start value. Specifies the number
of pixels after the leading edge of CLPIN to the Valid Pixel region.
11 0010
Test Pattern Width
0000 0000
[15:8]
Upper 8 bits of the Test Pattern Width value. Specifies, in
number of pixels, the width of the Valid Pixel region.
11 0011
Test Pattern Width
0000 0000
[7:0]
Lower 8 bits of the Test Pattern Width value. Specifies, in
number of pixels, the width of the Valid Pixel region.
11 0100
Test Pattern Control
0000 0000
[7:0]
Test Pattern Control Register.
[7]
Programmable Pattern Switch
0
Disabled. Normal LVDS output operation.
1
Enabled. AFE outputs LVDS test patterns.
[6:4]
Test Pattern Mode
000
Fixed Code
001
Horizontal Gradient Scan (Main Scan)
010
Vertical Gradient Scan (Sub Scan)
011
Grid Scan (Lattice Pattern)
100
Strip Pattern
101
LVDS Test Pattern. (Synchronous to CLPIN)
110
LVDS Test Pattern. (Asynchronous)
111
Not Used.
[3]
Pseudo Random Pattern Enable.
Overrides Programmable Patter Switch setting (bit 7).
Normally only one should be on.
[2]
Load Seed Enable.
When set, the seed value in the Test Pattern Value
Register is loaded in the LFSR at the leading edge of
CLPIN.
[1:0]
Test Pattern Output Channel Select.
00
Both Channels
01
Channel 1
10
Channel 2
11
Not Used
11 0101
Test Pattern Pitch
0000 0000
[7:0]
Test Pattern pitch, specifies number of pixels for H Gradient
pattern and Stripe pattern, or number of lines in the V Gradient
pattern, or specifies pixels & lines in the Lattice pattern.
45
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LM98640QML
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