參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 2/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Sub-
groups
Power Supply Specifications
IA
VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-4x
Powerdown Control Reg
= 0x00
(see Power Trimming section
for PGA and ADC Power
Trimming register settings)
5MHz
51.5
58
mA
1, 2, 3
15MHz
61.3
69
25MHz
69.6
79
40MHz
87.6
98
VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-8x
Powerdown Control Reg
= 0x00
(see Power Trimming section
for PGA and ADC Power
Trimming register settings)
5MHz
51.5
58
mA
1, 2, 3
15MHz
61.3
68
25MHz
72.9
82
40MHz
91.3
103
VDD33 Analog Supply Current
Single Channel
Power optimized for
PGA Gain = 1-4x
Powerdown Control Reg
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
(see Power Trimming section
for PGA and ADC Power
Trimming register settings)
5MHz
29.5
35
mA
1, 2, 3
15MHz
36.1
42
25MHz
42
47
40MHz
53.7
60
VDD33 Analog Supply Current
Single Channel
Power optimized for
PGA Gain = 1-8x
Powerdown Control Reg
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
(see Power Trimming section
for PGA and ADC Power
Trimming register settings)
5MHz
29.5
35
mA
1, 2, 3
15MHz
36.1
42
25MHz
43.8
50
40MHz
55.6
64
VDD33 Analog Supply Current
Powerdown
Powerdown Control Reg
= 0x80
2.85
3.85
mA
1, 2, 3
ID
VDD18 Digital Supply Current
LVDS Quad Lane Mode
LVDS Output Mode Reg
= 0x0E
5MHz
36
mA
15MHz
39
25MHz
42
40MHz
45
VDD18 Digital Supply Current
5MHz
23.5
29
mA
1, 2, 3
15MHz
25.5
31
25MHz
27.5
33
40MHz
30.5
37
VDD18 Digital Supply Current
Powerdown
Powerdown Control
Reg = 0x80
1.2
3.0
mA
1, 2, 3
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