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參數(shù)資料
| 型號(hào)： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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Output Mode 2 - Quad Lane
In Quad Lane mode each input channel is split into two data
lanes which are presented at 8X the pixel rate. The MSBs (bits
13 through 7) will be presented to one channel while the LSBs
(bits 6 through 0) will be presented to the other. A frame signal
is run at the pixel clock rate with the rising edge coincident
with the transition of the MSB of the data and the falling edge
coincident with the transition of bits 10 and 3 of the data lanes
for an odd output value, and coincident with the transition of
bits 11 and 4 for a even output value. A differential clock is
also output with rising edge transitions aligned within each
data eye. Data rates for Quad Lane mode range from
40Mbps, with a 5MHz clock, up to 320Mbps, with a 40MHz
clock.
30064753
FIGURE 15. Quad Lane LVDS Data Output Timing Diagram
LVDS Test Modes
The LVDS test modes present programmable data patterns
to the input of the LVDS serializer block. The type of pattern
is selectable through the Test Pattern Control register. Once
the LVDS test mode is enabled the patterns are output indef-
initely. Table 4 below shows the available test pattern modes.
TABLE 4. Test Pattern Modes
Test Pattern
Control[6:4]
Test Mode
000
Fixed Code
001
Horizontal Gradient
010
Vertical Gradient
011
Lattice Pattern
100
Strip Pattern
101
LVDS Test Pattern
(Synchronous)
110
LVDS Test Pattern
(Asynchronous)
111
Reserved
Each pattern consists of a Start Period and Valid Pixel region.
During the Start Period the output is the minimum code
(0x0000). The Valid Pixel region contains the selected Test
Pattern Mode output. The length (in pixels) of the Start period
is set using the Test Pattern Start register, and the width of
the Valid Pixel region is set using the Test Pattern Width reg-
ister.
To start the test pattern generation, enable Test Mode using
bit[1] of the Test and Scan Register (0x3D). Then load all pa-
rameters for the desired test pattern into the registers, and set
Pattern Enable bit of the Test Pattern Control Register (0x34).
Changing pattern parameters after the Pattern Enable bit is
set may result in undesired output. The pattern will start at the
next leading edge of CLPIN.
Test Mode 0 - Fixed Pattern
This test mode provides an LVDS output with a fixed value
output during the valid pixel region. The fixed value is set via
the Test Pattern Value registers. The Test Pattern Value reg-
ister is split into two registers the upper 6 bits of the test code
in first register, and the lower 8 bits of the test code in the
second.
Test Mode 1 - Horizontal Gradient
This mode provides LVDS data that progresses horizontally
from dark to light output values. This mode is highly variable,
allowing control over the starting value of the gradient, the
width of the gradient, and the increment rate of the gradient.
The starting value can be set in the Test Pattern Value reg-
ister, the width (in number of pixels) of each gradient step is
set via Test Pattern Pitch register, and increment rate (in LS-
Bs) is set via the Test Pattern Step register. When the LVDS
Horizontal Gradient test pattern is selected, the ramp begins
immediately and counts to the maximum value, and then re-
peats throughout the entire Valid Pixel region.
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LM98640QML
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