參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 21/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
Programmable Analog Offset
Correction
The LM98640QML provides two analog DACs per channel to
provide flexibility in offset control. Each channel has a Coarse
DAC and Fine DAC which have +/-8bit resolutions (8bit +
Sign). The two DACs can be used independently or as
Coarse/Fine configuration. The Coarse DAC provides a suf-
ficient range with moderate step sizes, while the Fine DAC is
for designs which need a finely tuned offset. The correction
voltage is applied to the "Video" level for both Sample & Hold
and CDS input modes. Because of the DACs location in the
signal path, the correction range lowers as CDS gain increas-
es, and the output referred correction steps and ranges in-
crease with PGA gain. Table 1 provides the range and step
size of each DAC.
TABLE 1. Analog Offset DAC Specifications
CDS/SH Gain
Range*
Step Size*
Output ADC Codes
Coarse DAC
1x
+/- 250mV
1mV
+/- 2048
2x
+/- 125mV
500V
+/- 2048
Fine DAC
1x
+/- 5mV
20V
+/- 41
2x
+/- 2.5mV
10V
+/- 41
*Referred to Input
To use the Offset Correction DACs, the Coarse DAC and Fine
DAC must be enabled using bits[6:5] of the Main Configura-
tion Register (0x00). Then the desired correction value should
be entered into the CDAC or FDAC register of the appropriate
channel. The Offset Correction DACs use a signed binary
format which is summarized in Table 2.
TABLE 2. Analog Offset Correction DAC Format
CDAC / FDAC Input Value
CDAC Correction (Codes) FDAC Correction (Codes)
1 1111 1111
+2048
+41
1 0111 1111
+1024
+20
0 1111 1111
0
0 0111 1111
-1024
-20
0 0000 0000
-2048
-41
Analog to Digital Converter
The LM98640QML has a 14bit Analog to Digital Converts
(ADC) for each channel. Each ADC has maximum and mini-
mum conversion rate of 40 MSPS and 5 MSPS per channel
respectively. The DNL performance is +/-0.5LSB and
+/-2LSB for INL for a 14bit out. The noise floor is -79dB at 2V
with a programmable gain of 0dB. If an out of range pixel is
presented to the ADC, the ADC will return to full compliance
within two cycles of the pixel clock.
www.national.com
28
LM98640QML
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