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參數(shù)資料
| 型號： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 22/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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LVDS Output
LVDS Output Voltage
The LM98640QML output data is presented in LVDS format.
Table 3 shows the available LVDS differential output voltage
(VOD) settings and its associated offset voltage (VOS).
TABLE 3. LVDS Differential Output Voltage Settings
VOD
VOS
250mV
1.2V
300mV
1.2V
350mV
1.1V
400mV
1.1V
LVDS Output Modes
The LM98640QML has a unique serial LVDS output format to
protect data transfer during ionizing doses. The format pro-
vides a buffer on either side of the data word, this is accom-
plished by clocking a 14bit word using a 16bit clock rate. In
the event of an ionizing dose that affects the DLL the output
clock period could fluctuate; with no buffer for the data word
this fluctuation could cause the loss of one or more of the data
word bits, but because the LM98640QML provides the buffer
the fluctuation does not cause any data loss. The data can
also be sent out in two modes: Dual or Quad Lane. The fol-
lowing sections describe these two modes.
TXFRM Output
The LM98640QML output includes a frame signal (TXFRM)
that should be used to locate the beginning and end of a par-
ticular pixel's serial data word. The rising edge of TXFRM is
coincident with the pixel's leading bit transition (TXOUT
MSB). This TXFRM rising edge can be detected by the cap-
turing FPGA or ASIC to mark the start of the serial data word.
In CDS mode, the input sampling amplifier has two physical
paths through which a particular pixel will be sampled. These
two sampling paths are a requirement in the Correlated Dou-
ble Sampling architecture. The sampling of the one pixel will
travel the first path (arbritrarily called an even pixel), and the
sampling of the next pixel will travel the second path (called
an odd pixel). The sampling will continue in an even/odd/
even/odd fashion for all pixels processed in a particular chan-
nel. Due to slight variances in the sampling paths (most
commonly a difference in switched capacitor matching), the
processing of identical pixels through the two different paths
may result in a small offset in ADC output data between the
two paths. To correct this, a simple digital offset can be ap-
plied in post processing to either the even pixel data or the
odd pixel data. To simplify this action, the LM98640QML will
indicate (with the TXFRM signal) whether the pixel traveled
the even path or the odd path. For all "Odd" pixels, the TXFRM
signal is high for three TXCLK periods. For "Even" pixels, the
TXFRM signal is high for two TXCLK periods. In Sample and
Hold Mode there is only one sampling path, therefore there is
no need to indicate an even or odd pixel. As a result, the
TXFRM signal is the same for every pixel in Sample and Hold
mode (i.e. high for three TXCLK periods).
Output Mode 1 - Dual Lane
In Dual Lane mode each input channel has its own data output
presented at 16X the pixel clock rate. A frame signal (TXFRM)
is output at the pixel clock rate with the rising edge occurring
coincident with the transition of the MSB of the data. In Sam-
ple/Hold Modes of operation, the falling edge is coincident
with the transition of bit 7 of the data. In CDS Mode, the falling
edge of TXFRM toggles between the ransition of bit 9 and bit
7 of the data. A differential clock is also output with transitions
aligned with the center of the data eye. Data rates for Dual
Lane mode range from 80Mbps, with a 5MHz clock, up to
640Mbps, with a 40MHz clock.
30064752
FIGURE 14. Dual Lane LVDS Output Timing Diagram
29
www.national.com
LM98640QML
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