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參數(shù)資料
| 型號(hào)： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 26/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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Power Trimming
The LM98640QML provides an adaptive power scaling fea-
ture that allows the user to optimize power consumption
based on the maximum operating frequency and the maxi-
mum amount of gain required. The power scaling mode is
selectable through the PGA Power Trimming and ADC Power
Trimming registers (0x02,0x03). The settings in these regis-
ters are common for both channels PGA and ADC. Using
these registers the user can control the current of the two
stages of the PGA, and the current for the two levels of the
ADC. The following table provides a set of baseline configu-
rations for various operating frequencies and gain ranges.
These configurations should be treated as baseline values
and can be tuned to your specific application.
Operating
Frequency
1-4x Max PGA Gain
1-8x Max PGA Gain
5 - 15 MSPS
PGA Power Trimming = 0x00
PGA Power Trimming = 0x01
ADC Power Trimming = 0x00
15 - 25 MSPS
PGA Power Trimming = 0x01
ADC Power Trimming = 0x00
PGA Power Trimming = 0x09
ADC Power Trimming = 0x00
25 - 40 MSPS
PGA Power Trimming = 0x01
ADC Power Trimming = 0x08
PGA Power Trimming = 0x09
ADC Power Trimming = 0x08
Powerdown Modes
The LM98640QML provides several ways to save power
when the device is not in normal usage mode. Using the Pow-
erdown Control Register (0x01) the part can be placed into
Powerdown Mode, or Single Channel Mode. In Powerdown
Mode (Powerdown Control, bit[7]) the following blocks are
placed in a Powerdown mode: VCLP, Channel 1 & 2 Refer-
ence Buffers, Channel 1 & 2 PGA OpAmps, and Channel 1 &
2 Amplifiers. Powerdown Mode will override all other Power-
down Control Register bits. To place the part in Single Chan-
nel Mode each block of the unused channel can be powered
down using their respective control bits (Powerdown Control,
bits[5:0]). If an external reference clamp is used the VCLP
block can be powered down during any Power mode. For ap-
plications operating at a low enough frequency additional
power can be saved by powering down one channel reference
buffer, then externally tie both channel's reference pins to-
gether.
www.national.com
32
LM98640QML
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