參數(shù)資料
型號: LM98640W-MPR
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, CQFP68
封裝: CERAMIC, QFP-68
文件頁數(shù): 3/50頁
文件大?。?/td> 1688K
代理商: LM98640W-MPR
Symbol
Parameter
Conditions
Notes
Typical
Min
Max
Units
Sub-
groups
PWR
Average Power Dissipation
Power optimized for
PGA Gain = 1-4x
Dual Channel
LVDS Dual Lane Mode
5MHz
212
244
mW
1, 2, 3
15MHz
250
284
25MHz
280
320
40MHz
345
390
Average Power Dissipation
Power optimized for
PGA Gain = 1-8x
Dual Channel
LVDS Dual Lane Mode
5MHz
212
244
mW
1, 2, 3
15MHz
250
284
25MHz
290
330
40MHz
356
407
PSRR
Dynamic Power Supply Rejection
Ratio
CDS Gain = 1x
PGA Gain = 1x
200 mVpp, 200 KHz
-72.3
dB
200 mVpp, 500 KHz
-72
200 mVpp, 1 MHz
-71
200 mVpp, 1.5 MHz
-68
200 mVpp, 2 MHz
-66
Internal Reference Specifications
V
REFBG
Reference Voltage
1.218
V
Reference Tolerance
(chip to chip)
±2
%
R
REFBG
Reference Impedance
20
k
V
REFTC
Temperature Coefficient
25°C to 125°C
80
ppm/°
C
-55°C to 25°C
50
Input Sampling Circuit Specifications
V
IN
Input Voltage Level
CDS Gain=1x, PGA Gain=1x
2
Vp-p
1, 2, 3
CDS Gain=2x, PGA Gain=1x
1
CDS Gain=1x, PGA
Gain=0.7x
2.85
V
RESET
Reset Feed Through
500
mV
I
IN_SH
Sample and Hold Mode
Input Leakage Current
CDS Gain = 1x
384
μA
OS
X = VDD33 (OSX = VSS)
CDS Gain = 2x
-475
A
OS
X = VDD33 (OSX = VSS)
C
SH
Sample/Hold Mode
CDS Gain = 1x
4
pF
Equivalent Input Capacitance
(see Figure 10)
CDS Gain = 2x
8
pF
I
IN_CDS
CDS Mode
OS
X = VDD33 (OSX = VSS)
300
nA
Input Leakage Current
R
CLPIN
CLPIN Switch Resistance
16
(OS
X to VCLP Node in Figure 7)
VCLP Reference Circuit Specification
VCLP DAC Resolution
5
5
Bits
1, 2, 3
VCLP DAC Step Size
98
96
102
mV
1, 2, 3
V
VCLP
VCLP DAC Voltage Min Output
VCLP Control Register =
224
194
298
mV
1, 2, 3
0110 0000
VCLP DAC Voltage Max Output
VCLP Control Register =
3.07
2.99
3.11
V
1, 2, 3
0111 1101
I
SC
VCLP DAC Short Circuit Output
Current
VCLP Control Register =
33
mA
011x xxxx
11
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