參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 25/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
Test Mode 2 - Vertical Gradient
This mode is similar to the Horizontal Gradient, only the gra-
dient is in the vertical direction. See the Horizontal Gradient
mode description for details.
Test Mode 3 - Lattice Pattern
This mode provides LVDS data that creates a lattice grid. The
lattice is made of dark lines on a light background. The line
output value is set by Test Pattern Step register, and back-
ground value is set by Test Pattern Value register. The num-
ber of pixels & lines in the lattice is set via Test Pattern Pitch
register.
Test Mode 4 - Stripe Pattern
This mode provides LVDS data that creates a vertical stripe
pattern. The stripe pattern is made of dark and light lines. The
output value of the dark portion is set via Test Pattern Step
register, and the light portion is set via Test Pattern Value
register. The stripe width in pixels is set via Test Pattern Pitch
register.
Test Mode 5 - LVDS Test Pattern (Synchronous)
This mode provides an LVDS output with a fixed value re-
peated continuously. The pattern starts at the leading edge of
CLPIN. The fixed value is set via the Test Pattern Value reg-
isters. The Test Pattern Value register is split into two regis-
ters the upper 8 bits of the test code in first register, and the
lower 8 bits of the test code in the second. This is useful for
system debugging of the LVDS link and receiver circuitry.
Test Mode 6 - LVDS Test Pattern (Asynchronous)
This mode provides an LVDS output with a fixed value re-
peated continuously. The pattern starts asynchronously with-
out CLPIN. The fixed value is set via the Test Pattern Value
registers. The Test Pattern Value register is split into two reg-
isters the upper 8 bits of the test code in first register, and the
lower 8 bits of the test code in the second. This is useful for
system debugging of the LVDS link and receiver circuitry.
Psuedo Random Number Mode
This mode provides LVDS data produced from the following
polynomial:
P(x) = X14 + X13 + X11 + X9 + 1
To start the Psuedo Random Number mode, set the Test
Mode bit of the Test and Scan Register. Then load the seed
value in the Test Pattern Value register, and set the Psuedo
Random Enable bit of the Test Pattern Control register. The
pattern will start outputting after the next leading edge of
CLPIN.
Clock Receiver
A differential clock receiver is used to generate all clock sig-
nals on the LM98640QML. The clock input should be exter-
nally terminated with 100 Ohms between the input clock pins.
The clock may be DC or AC coupled to the AFE.
31
www.national.com
LM98640QML
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