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參數(shù)資料
| 型號： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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30064709
FIGURE 8. Typical CCD Waveform and LM98640QML Input Clamp Signal (CLPIN)
Sample and Hold Mode Biasing
Proper DC biasing of the CCD waveform in Sample and Hold
mode is critical for realizing optimal operating conditions. In
Sample/Hold Mode, the DC bias point of the input pin is typ-
ically set by actuating the input clamp switch (see Figure 7)
during optical black pixels which connects the input pins to
the VCLP pin DC voltage. The signal controlling this switch is
CLPIN. CLPIN is an external signal connected on the CLPIN
pin.
Actuating the input clamp will force the average value of the
CCD waveform to be centered around the VCLP DC voltage.
During Optical Black Pixels, the CCD output has roughly three
components. The first component of the pixel is a “Reset
Noise” peak followed by the Reset (or Pedestal) Level volt-
age, then finally the Black Level voltage signal. Taking the
average of these signal components will result in a final
“clamped” DC bias point that is close to the Black Level signal
voltage.
To provide a more precise DC bias point (i.e. a voltage closer
to the Black Level voltage), the CLPIN pulse can be “gated”
by the internally generated CLAMP clock. This resulting
CLPIN
GATED signal is the logical “AND” of the CLAMP and
CLPIN signals as shown in Figure 8. By using the CLPIN
GAT-
ED signal, the higher Reset Noise peak will not be included in
the clamping period and only the Pedestal Level components
of the CCD waveform will be centered around VCLP.
30064710
FIGURE 9. Sample and Hold Mode Simplified Input
Diagram
In Sample and Hold Mode, the impedance of the analog input
pins is dominated by the switched capacitance of the CDS/
Sample and Hold amplifier. The amplifier switched capaci-
tance, shown as C
S in Figure 9, and internal parasitic capac-
itances can be estimated by a single capacitor switched
between the analog input and the VCLP reference pin for
Sample and Hold mode. During each pixel cycle, the modeled
capacitor, C
SH, is charged to the OSX+ minus OSX- voltage
then discharged. The average input current at the OS
X- pin
can be calculated knowing the input signal amplitude and the
frequency of the pixel.
25
www.national.com
LM98640QML
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