參數(shù)資料
型號： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 13/50頁
文件大?。?/td> 1688K
代理商： LM98640W-MPR
System Overview
Introduction
The LM98640QML is a 14-bit, 5MSPS to 40MSPS, dual chan-
nel, complete Analog Front End (AFE) for digital imaging
applications. The system block diagram of the LM98640QML,
shown in Figure 4 highlights the main features of the device.
Each input has its own Input Bias and Clamping Network and
Correlated Double Sample (CDS) amplifier (which can also
be configure to operate in Sample/Hold Mode). Two +/-8Bit
Offset DACs apply independent coarse and fine offset cor-
rection for each channel. A -3 to 18dB Programmable Gain
Amplifier (PGA) applies independent gain correction for each
channel. The signals are digitized using two independent on
chip high performance 14-bit, 40MHz analog-to-digital con-
verters. The data is finally output using a unique Serial LVDS
output format that prevents data loss during any ionizing dos-
es.
Input Sampling Modes
The LM98640QML provides two input sampling modes, Sam-
ple & Hold mode and Correlated Double Sample (CDS) mode.
The following sections describe these two input sampling
modes.
Sample & Hold Mode
In Sample/Hold mode, a Video Level signal and a Reference
Level signal need to be presented to the LM98640QML. The
Reference Level signal must be connected to the OS
X+ pin,
and the Video Level signal connected to the OS
X- pin. The
output code will then be OS
X+ minus OSX-, or the difference
between the Reference Level and Video Level. A minimum
code represents zero deviation between the Reference and
Video Levels and a maximum code represents a 2V deviation
between the Reference and Video Levels with CDS and PGA
gains of 1x.
The Reference Level signal can be either an external signal
from the image sensor, or the VCLP pin can be externally
connected to the OS
X+ pin. In order to fully utilize the range
of the input circuitry it is desirable to cause the Black Level
signal voltage to be as close to the Reference Level voltage
as possible, resulting in a near zero scale output for Black
Level pixels. The LM98640QML provides several methods for
ensuring the Black Level signal and Reference Level are
matched, these are described in the Input Bias and Clamp-
ing section.
To place the LM98640QML in Sample & Hold Mode from
power up, first write the baseline configuration to the registers
as shown in the Configuration Registers section. This config-
uration has Sample & Hold mode enabled by default. Next,
the SAMPLE pulse must be properly positioned over the input
signal using the CLAMP/SAMPLE Adjust.
Sample & Hold Mode CLAMP/SAMPLE Adjust
For accurate sampling of the input signals the LM98640QML
allows for full adjustment of the internal SAMPLE pulse to
align it to the proper positions over the input signal. In Sample
& Hold mode the SAMPLE pulse should be placed over the
pixel output period of the image sensor. Only the Sample Start
and Sample End Registers (0x22,0x23) need to be config-
ured, the Clamp Start and Clamp End Registers (0x20,0x21)
are not valid in Sample & Hold Mode. Internally the input clock
is divided into 64 edges per clock period, the Sample Start
and Sample End Registers correspond to the internal edge
number the SAMPLE pulse will start and end. To adjust the
SAMPLE pulse, first send the CLAMP and SAMPLE signals
to the DTM pins by writing 10 to bits[4:3] of the Clock Monitor
Register (0x09). This will allow the user to observe the SAM-
PLE pulse on pin DTM1 along with the image sensor output
using an oscilloscope. Then, using the Sample Start and End
Registers, adjust the SAMPLE pulse to align it over the Video
Level portion of the image sensor output. To allow for settling
and to reduce noise, the SAMPLE pulse should be made as
wide as possible and fill the entire Video Level portion of the
input signal.
Figure 5 shows some examples of an input waveform and
where the SAMPLE pulse should be placed. Ideally the image
sensor output would line up directly with the input clock at the
AFE inputs, but due to trace delays in the system the image
sensor output is delayed relative to the input clock. In the de-
layed image sensor waveform the Sample Start value is
higher than the Sample End value. In this situation the SAM-
PLE pulse will start in one clock period and wraps around to
the next. This allows the LM98640QML to adjust for the delay
in the image sensor waveform. Notice that edge zero of the
internal clock does not line up with the rising edge of the input
clock. This is due to internal delays of the clock signals. The
amount of delay can be calculated from operating frequency
using the following formula: t
DCLK = 6.0ns + 3/64 * TINCLK
www.national.com
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LM98640QML
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