參數(shù)資料
型號(hào): LM98640W-MPR
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, CQFP68
封裝: CERAMIC, QFP-68
文件頁(yè)數(shù): 30/50頁(yè)
文件大小: 1688K
代理商: LM98640W-MPR
Configuration
Registers
need
to
be
written
with
baseline
values
after
power-up
to
place
part
in
a
valid
state.
Address
(Binary)
Register
Title
(Mnemonic)
Baseline
(Binary)
Register/Bit
Description
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Analog
Configuration
00
0000
Main
Configuration
0000
0100
Not
Used
Coarse
DAC
Enable
Fine
DAC
Enable
Reserved
CLPIN
Gating
Enable
CDS
Gain
Enable
Reserved
CDS
Enable
00
0001
Powerdown
Control
0000
Master
Powerdown
VCLP
Powerdown
Ch2
Ref
Buf
Powerdown
Ch1
Ref
Buf
Powerdown
Ch2
PGA
Powerdown
Ch1
PGA
Powerdown
Ch2
ADC
Powerdown
Ch1
ADC
Powerdown
00
0010
PGA
Power
Trimming
0010
0100
Reserved
PGA
Stage
2
Bias
Current
Trimming
PGA
Stage
1
Bias
Current
Trimming
00
0011
ADC
Power
Trimming
0101
1011
Reserved
ADC
Current
Trimming
2
ADC
Current
Trimming
1
00
0100
VCLP
Control
0111
0100
Not
Used
Buffer
Enable
VCLP
Enable
VCLP
Voltage
Level
00
0101
LVDS
Output
Modes
0000
1110
Clear
Reserved
Quad
Lane
Enable
LVDS
Enable
LVDS
Control
00
0110
Sample
&
Hold
1000
0001
S/H
Enable
Not
Used
Ref
Buf
Power
Level
Reserved
00
0111
Status
0000
Not
Used
False
Lock
00
1000
Reserved
0000
Reserved
00
1001
Clock
Monitor
0000
Not
Used
Enable/Select
Not
Used
00
1010
Reserved
0000
Not
Used
00
1011
Reserved
0000
Not
Used
00
1100
Reserved
0000
Not
Used
00
1101
Reserved
0000
Not
Used
00
1110
Reserved
0000
Not
Used
00
1111
Reserved
0000
Not
Used
Gain
&
Offset
DAC
Configuration
01
0000
CDAC1
0000
Not
Used
Offset
bit
8
01
0001
CDAC1
1111
Offset
Value
bits
7:0
01
0010
FDAC1
0000
Not
Used
Offset
bit
8
01
0011
FDAC1
1111
Offset
Value
bits
7:0
01
0100
Reserved
0000
Not
Used
01
0101
PGA1
0110
0001
PGA
Gain
Value
01
0110
Reserved
0000
Not
Used
01
0111
Reserved
0000
Not
Used
01
1000
CDAC2
0000
Not
Used
Offset
Bit
8
01
1001
CDAC2
1111
Offset
Value
bits
7:0
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