參數(shù)資料
型號(hào)： LM98640W-MPR
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 37/50頁
文件大小： 1688K
代理商： LM98640W-MPR
Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
00 0101
LVDS Output Modes
0000 1110
[7:0]
LVDS Output Configuration Register.
[7]
Serializer Data Reset. (Not self-clearing)
[6:4]
Not Used.
[3]
LVDS Output Mode
0
Dual Lane Mode (see )
1
Quad Lane Mode (see )
[2]
LVDS Driver Enable.
0
LVDS Drivers Disabled
1
LVDS Drivers Enabled
(Note: In Dual Lane Mode TX0 and TX3 are disabled
regardless of driver enable)
[1:0]
LVDS Amplitude and Common Mode Voltage.
00
250mV (1.2V DC Offset)
01
300mV (1.2V DC Offset)
10
350mV (1.1V DC Offset)
11
400mV (1.1V DC Offset)
00 0110
Sample & Hold
1000 0001
[7:0]
Sample & Hold Mode Register
[7]
Sample & Hold Mode Enable
0
Disabled.
1
Enabled.
[6:3]
Not Used.
[2:1]
Reference Buffer Power Level
11
100% Power. Used for F
INCLK = 20-40MHz.
10
60% Power. Used for F
INCLK = 10-20MHz.
01
60% Power. Used for F
INCLK = 10-20MHz.
00
30% Power. Used for F
INCLK = 5-10MHz.
[0]
Reserved.
00 0111
Status
0000 0000
[7:0]
Status Register. (Read Only)
[7:1]
Not Used.
[0]
False Lock Detect.
Indicates if DLL is locked into a half frequency state.
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LM98640QML
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