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參數(shù)資料
| 型號： | LM98640W-MPR |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 38/50頁 |
| 文件大?。?/td> | 1688K |
| 代理商： | LM98640W-MPR |
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Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
00 1001
Clock Monitor
0000 0000
[7:0]
Internal Clock Signal Monitor Register
[7:5]
Not Used.
[4:3]
Enable and select clocks to be monitored on the Digital Timing
Monitor. (DTM)
00
Disable Digital Timing Monitor Pins (DTM0, DTM1)
01
Send CLAMP
EVEN to DTM0 pin, and SAMPLEEVEN to DTM1
10
Send CLAMP
ODD to DTM0 pin, and SAMPLEODD to DTM1
11
Send ODD tag and ADC Clock to the DTM.
[2:0]
Reserved. Set to 000.
Register Definitions - GAIN & Offset DAC Configuration
Registers need to be written with baseline values after power-up to place part in a valid state.
Address
(Binary)
Register Title
Baseline
(Binary)
Bit(s)
Description
01 0000
CDAC1
0000 0000
[7:0]
Channel 1 Coarse DAC Register.
[7:1]
Not Used.
[0]
Bit 8 of Channel 1 Coarse DAC Offset Value.
01 0001
CDAC1
1111 1111
[7:0]
Channel 1 Coarse DAC Offset Value bits 7:0.
01 0010
FDAC1
0000 0000
[7:0]
Channel 1 Fine DAC Register.
[7:1]
Not Used.
[0]
Bit 8 of Channel 1 Fine DAC Offset Value.
01 0011
FDAC1
1111 1111
[7:0]
Channel 1 Fine DAC Offset Value bits 7:0.
01 0101
PGA1
0110 0001
[7:0]
Channel 1 Programmable Gain Amplifier Value.
01 1000
CDAC2
0000 0000
[7:0]
Channel 2 Coarse DAC Register.
[7:1]
Not Used.
[0]
Bit 8 of Channel 2 Coarse DAC Offset Value.
01 1001
CDAC2
1111 1111
[7:0]
Channel 2 Coarse DAC Offset Value bits 7:0.
01 1010
FDAC2
0000 0000
[7:0]
Channel 2 Fine DAC Register.
[7:1]
Not Used.
[0]
Bit 8 of Channel 2 Fine DAC Offset Value.
01 1011
FDAC2
1111 1111
[7:0]
Channel 2 Fine DAC Offset Value bits 7:0.
01 1100
PGA2
0110 0001
[7:0]
Channel 2 Programmable Gain Amplifier Value.
43
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LM98640QML
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