參數(shù)資料
型號(hào)： GE28F640W30TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝： 0.75 MM PITCH, VFBGA-56
文件頁(yè)數(shù)： 66/104頁(yè)
文件大?。?/td> 1443K
代理商： GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
64
Order Number: 290702, Revision: 011
11.3.1
EFP Requirements and Considerations
11.3.2
Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions
from a 1 to a 0, indicating that the WSM is busy with EFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP
level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1]
are set, and the EFP operation terminates.
Note:
After the EFP Setup and Confirm command sequence, reads from the flash device automatically
output status register data. Do not issue the Read Status Register command, because this command
is interpreted as data to program at WA0.
11.3.3
Program
After setup completion, the host programming system must check SR[0] to determine the
data-stream ready status (SR[0]=0). Each subsequent write after this check is a program-data write
to the flash memory array. Each cell within the memory word to be programmed to 0 receives one
WSM pulse; additional pulses, if required, occur in the verify phase.
SR[0]=1 indicates that the WSM is busy applying the program pulse.
The host programmer must poll the flash device status register for the program done state after
each data-stream write.
SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location have
received their single WSM program pulse, and that the flash device is ready for the next word.
Although the host can check full status for errors at any time, this check is necessary only on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside of the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
Table 24.
EFP Requirements and Considerations
EFP Requirements
EFP Considerations
Ambient temperature: TA = 25 °C ±5 °C
Block cycling below 100 erase cycles
1
VCC within specified operating range
RWW not supported2
VPP within specified VPPH range
EFP programs one block at a time
Target block unlocked
EFP cannot be suspended
1.
Recommended for optimum performance. Some degradation in
performance might occur if this limit is exceeded, but the internal
algorithm will continue to work properly.
2.
Code or data cannot be read from another partition during EFP.
相關(guān)PDF資料
PDF描述
GEN12.5-120 Programmable DC Power Supplies 750W/1500W
GEN12.5-60 Programmable DC Power Supplies 750W/1500W
GFL750 COPPER ALLOY, WIRE TERMINAL
GFL500 COPPER ALLOY, WIRE TERMINAL
GFL350 COPPER ALLOY, WIRE TERMINAL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GE28F800B3BA90 制造商:Intel 功能描述:NOR Flash, 512K x 16, 45 Pin, Plastic, BGA
GE28F800B3TA90 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Advanced Boot Block Flash Memory
GE28F800C3BA70 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
GE28F800C3BA90 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
GE28F800C3BC70 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*