參數(shù)資料
型號(hào)： GE28F640W30TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝： 0.75 MM PITCH, VFBGA-56
文件頁(yè)數(shù)： 2/104頁(yè)
文件大?。?/td> 1443K
代理商： GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
10
Order Number: 290702, Revision: 011
2.0
Functional Overview
This section provides an overview of the W30 flash memory device features and architecture.
2.1
Overview
The W30 flash memory device provides Read-While-Write (RWW) and Read-White-Erase (RWE)
capability. This capability provides high-performance synchronous and asynchronous reads in
package-compatible densities using a 16-bit data bus. Individually-erasable memory blocks are
optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the
parameter partition at either the top or bottom of the memory map. The rest of the memory array is
grouped into 32-Kword main blocks.
The memory architecture for the W30 flash memory device consists of multiple 4-Mbit partitions,
the exact number depending on the flash device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read operations. Burst
reads can traverse partition boundaries, but user application code is responsible for ensuring that
burst reads do not extend into a partition that is actively programming or erasing. Although each
partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or
erase in one partition while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of the W30 flash
memory device. An erase can be suspended to perform a program or read operation within any
block, except a block that is erase-suspended. A program operation nested within a suspended
erase can subsequently be suspended to read yet another memory location.
After power-up or reset, the W30 flash memory device defaults to asynchronous read
configuration. Writing to the flash memory device Read Configuration Register (RCR) enables
synchronous burst-mode read operation. In synchronous mode, the CLK input increments an
internal burst address generator. CLK also synchronizes the flash memory device with the host
CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A
programmable WAIT output signals to the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the W30 flash memory device incorporates
Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power
designs. The EFP feature provides fast program performance, which can increase the
manufacturing throughput of a factory.
The W30 flash memory device supports read operations at 1.8 V and erase and program operations
at 1.8 V or 12 V. With the 1.8-V option, VCC and VPP can be tied together for an ultra-low-power
design. In addition to voltage flexibility, the dedicated VPP input provides extensive data
protection when VPP < VPPLK.
A 128-bit protection register can implement new security techniques and data protection schemes:
A combination of factory-programmed and user-OTP data cells provide unique flash device
identification, help implement fraud or cloning prevention schemes, or help protect content.
Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data.
An additional block lock-down capability provides hardware protection where software
commands alone cannot change the block protection status.
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