參數(shù)資料
型號: GE28F640W30TD70
廠商: INTEL CORP
元件分類: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝: 0.75 MM PITCH, VFBGA-56
文件頁數(shù): 51/104頁
文件大?。?/td> 1443K
代理商: GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
50
Order Number: 290702, Revision: 011
9.0
Flash Device Operations
This chapter provides an overview of flash device operations. The W30 flash memory device
family includes an on-chip Write State Machine (WSM) to manage block erase and program
algorithms. The WSM Command User Interface (CUI) allows minimal processor overhead with
RAM-like interface timings.
9.1
Bus Operations
9.1.1
Read
The W30 flash memory device has several read configurations:
Asynchronous page mode read.
Synchronous burst mode read — outputs four, eight, sixteen, or continuous words, from main
blocks and parameter blocks.
Several read modes are available in each partition:
Read-array mode: read accesses return flash memory array data from the addressed
locations.
Read identifier mode: reads return manufacturer and device identifier data, block lock status,
and protection register data. Identifier information can be accessed starting at a 4-Mbit
partition base addresses; the flash memory array is not accessible in read identifier mode.
Read query mode: reads return the flash device CFI data. CFI information can be accessed
starting at a 4-Mbit partition base addresses; the flash memory array is not accessible in read
query mode.
Read status register mode: reads return status register data from the addressed partition. The
array data for that partition is not accessible. A system processor can check the status register
to determine the state of an addressed partition, or to monitor program and erase progress.
Table 17.
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
Notes
Read
Asynchronous
VIH
X
L
H
Asserted
Output
-
Synchronous
VIH
Running
L
H
Driven
Output
1
Burst Suspend
VIH
Halted
X
L
H
Active
Output
-
Write
VIH
X
L
H
L
Asserted
Input
2
Output Disable
VIH
XX
L
H
Asserted
High-Z
3
Standby
VIH
XX
H
X
High-Z
3
Reset
VIL
XX
X
High-Z
3,4
Notes:
1.
WAIT is valid only during synchronous array-read operations.
2.
Refer to the Table 19, “Bus Cycle Definitions” on page 55 for valid DQ[15:0] during a write operation.
3.
X = Don’t Care (H or L).
4.
RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
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