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參數資料
| 型號： | GE28F640W30TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, VFBGA-56 |
| 文件頁數： | 40/104頁 |
| 文件大?。?/td> | 1443K |
| 代理商： | GE28F640W30TD70 |
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28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
40
Order Number: 290702, Revision: 011
7.3
AC Write Characteristics
Table 13.
AC Write Characteristics
#
Sym
Parameter 1,2
Notes
32-Mbit
64-Mbit
128-Mbit
Unit
-70
-85 / -90
MinMax
W1
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Low
150
-
150
-
ns
W2
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Low
0
-
0
-
ns
W3
tWLWH (tELEH)
WE# (CE#) Write Pulse Width Low
45
-
60
-
ns
W4
tDVWH (tDVEH)
Data Setup to WE# (CE#) High
45
-
60
-
ns
W5
tAVWH (tAVEH)
Address Setup to WE# (CE#) High
45
-
60
-
ns
W6
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
-
0
-
ns
W7
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
0
-
0
-
ns
W8
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
0
-
0
-
ns
W9
tWHWL (tEHEL)
WE# (CE#) Pulse Width High
25
-
25
-
ns
W10
tVPWH (tVPEH)
VPP Setup to WE# (CE#) High
200
-
200
-
ns
W11
tQVVL
VPP Hold from Valid SRD
0-
0
-
ns
W12
tQVBL
WP# Hold from Valid SRD
0-
0
-
ns
W13
tBHWH (tBHEH)
WP# Setup to WE# (CE#) High
200
-
200
-
ns
W14
tWHGL (tEHGL)
Write Recovery before Read
-
0
-
0
-
ns
W16
tWHQV
WE# High to Valid Data
3,6,10
t
AVQV
+ 40
-
t
AVQV
+ 50
-ns
W18
tWHAV
WE# High to Address Valid
3,9,10
0
-
0
-
ns
W19
tWHCV
WE# High to CLK Valid
3,10
20
-
20
-
ns
W20
tWHVH
WE# High to ADV# High
3,10
20
-
20
-
ns
Notes:
1.
Write timing characteristics during erase suspend are the same as during write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
6.
System designers must take this into account, and can insert a software No-Op instruction to delay the first read after
issuing a command.
7.
For commands other than resume commands.
8.
VPP must be held at VPPL or VPPH until block erase or program success is determined.
9.
Applicable during asynchronous reads following a write.
10.
tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH
both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs
first).
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