參數(shù)資料
型號： GE28F640W30TD70
廠商： INTEL CORP
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝： 0.75 MM PITCH, VFBGA-56
文件頁數(shù)： 20/104頁
文件大?。?/td> 1443K
代理商： GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
June 2005
Intel Wireless Flash Memory (W30)
Datasheet
22
Order Number: 290702, Revision: 011
VSSQ
Power
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal can be tied
directly to VSS.
DU
—
DO NOT USE: Do not use this pin. Do not connect this pin to any power supplies, signals, or other
pins; this pin must be floated.
NC
—
NO CONNECT: No internal connection; can be driven or floated.
Table 6.
Signal Descriptions - QUAD+ Package (Sheet 1 of 3)
Symbol
Type
Description
A[MAX:MIN]
Input
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
128-Mbit Die : AMAX = A22
64-Mbit Die : AMAX = A21
32-Mbit Die : AMAX = A20
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future flash device densities.
DQ[15:0]
Input/
Output
DATA INPUTS/OUTPUTS:
Inputs data and commands during write cycles.
Outputs data during read cycles.
Data signals float when the flash device or its outputs are deselected. Data are internally latched
during writes on the flash device.
F[3:1]-CE#
Input
FLASH CHIP ENABLE: Low-true input.
F[3:1]-CE# low selects the associated flash memory die.
When asserted, flash memory internal control logic, input buffers, decoders, and sense amplifiers
are active.
When deasserted, the associated flash die is deselected, power is reduced to standby levels, and
data and WAIT outputs are placed in high-Z state.
F1-CE# selects or deselects flash die #1.
F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die.
F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two
flash dies.
S-CS1#
S-CS2
Input
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).
When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input
buffers, decoders, and sense amplifiers are active.
When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its
power is reduced to standby levels.
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked
combinations without SRAM die.
P[2:1]-CS#
Input
PSRAM CHIP SELECT: Low-true input.
When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are
active.
When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die.
This ball is an RFU on stacked combinations without PSRAM.
P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM
dies. This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM.
Table 5.
Signal Descriptions - BGA Package & VF BGA Package (Sheet 2 of 2)
Symbol
Type
Name and Function
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