參數(shù)資料
型號(hào): GE28F640W30TD70
廠商: INTEL CORP
元件分類(lèi): PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA56
封裝: 0.75 MM PITCH, VFBGA-56
文件頁(yè)數(shù): 65/104頁(yè)
文件大?。?/td> 1443K
代理商: GE28F640W30TD70
28F640W30, 28F320W30, 28F128W30
Datasheet
Intel Wireless Flash Memory (W30)
June 2005
Order Number: 290702, Revision: 011
63
11.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When VPP is at VPPL, program and erase currents are drawn through
VCC. If VPP is driven by a logic signal, VPPL must remain above the VPPLMin value to perform
in-system flash memory modifications. When VPP is connected to a 12 V power supply, the flash
device draws program and erase current directly from VPP, which eliminates the need for an
external switching transistor to control the VPP voltage.
device power supply usage in various configurations.
The 12-V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes. However, this mode is not intended for extended use.12 V can
be applied to VPP during program and erase operations as specified in Section 5.2, “Operating
Conditions” on page 26. VPP can be connected to 12 V for a total of tPPH hours maximum.
Stressing the flash device beyond these limits might cause permanent damage.
11.3
Enhanced Factory Program (EFP)
EFP substantially improves flash device programming performance through a number of
enhancements to the conventional 12-Volt word program algorithm. The more efficient WSM
algorithm in EFP eliminates the traditional overhead delays of the conventional word program
mode in both the host programming system and the flash device. Changes to the conventional word
programming flowchart and internal WSM routine were developed because of today's beat-rate-
sensitive manufacturing environments; a balance between programming speed and cycling
performance was attained.
The host programmer writes data to the flash device and checks the Status Register to determine
when the data has completed programming. This modification cuts write bus cycles approximately
in half.
Following each internal program pulse, the WSM increments the flash device address to the
next physical location.
Programming equipment can then sequentially stream program data throughout an entire block
without having to setup and present each new address.
In combination, these enhancements reduce much of the host programmer overhead, enabling more
of a data streaming approach to flash device programming.
EFP further speeds up programming by performing internal code verification. With this feature,
PROM programmers can rely on the flash device to verify that it has been programmed properly.
From the flash device side, EFP streamlines internal overhead by eliminating the delays previously
associated with switching voltages between programming and verify levels at each memory-word
location.
EFP consists of four phases: setup, program, verify, and exit. Refer to Figure 29, “Enhanced
Factory Program Flowchart” on page 66 for a detailed graphical representation of how to
implement EFP.
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