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| 型號(hào)： | EDX5116ADSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 512M比特的XDR DRAM的⑩ |
| 文件頁數(shù)： | 63/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE |
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Data Sheet E1033E30 (Ver. 3.0)
63
EDX5116ADSE
t
RR
Row-to-row time: interval between ROWA-ACT or ROWP- t
REFA or ROWP-REFI activate commands to different banks. t
RR
4
4
4
4
4
4
4
4
t
CYCLE
Figure 4 -
Figure 7
t
RCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-
RD read command to the same bank.
5
7
7
9
t
CYCLE
Figure 4 -
Figure 7
t
RCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate t
command and a COL-WR or COL-WRM write command to the same bank. t
RCD-W ERAW
1
5
3
7
3
7
5
9
t
CYCLE
Figure 4 -
Figure 7
t
CAC
Column access delay: interval from COL-RD read command to Q read data
6
7
7
8
t
CYCLE
Figure 10
t
CWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write
data.
3
3
3
3
t
CYCLE
Figure 9
t
CC
Column-to-column time: interval between successive COL-RD commands, or between suc-
cessive COL-WR or COLM-WRM commands.
2
2
2
2
t
CYCLE
Figure 4 -
Figure 7
t
RW-BUB,
Read-to-write bubble time: interval between the end of a Q read data packet and the start of
D write data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
3
t
CYCLE
Figure 13
t
WR-BUB,
Write-to-read bubble time: interval between the end of a D writed data and the start of Q
read data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
4
t
CYCLE
Figure 13
t
Δ
RW
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-
WRM write command.
d
8
9
9
9
t
CYCLE
Figure 12
t
Δ
WR
Write-to-read time: interval between a COL-WR or t
Δ
WR
COLM-WRM write command and a COL-RD read command. t
Δ
WR-De
9
2
10
2
10
2
10
2
t
CYCLE
Figure 12
t
RDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE pre-
charge command to the same bank.
3
4
4
6
t
CYCLE
Figure 4 -
Figure 7
t
WRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and
a ROWP-PRE precharge command to the same bank.
10
12
12
14
t
CYCLE
Figure 4 -
Figure 7
t
DR
Write data-to-read time: interval between the start of D write data and a COL-RD read com-
mand to the same bank.
6
7
7
7
t
CYCLE
Figure 12
t
DP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge com-
mand to the same bank.
7
9
9
11
t
CYCLE
Figure 9
t
LRRn-LRRn
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command.
f
16
20
24
24
t
CYCLE
Table 4
t
REFx-LRRn
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
16
20
24
24
t
CYCLE
Table 4
t
LRRn-REFx
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
16
20
24
24
t
CYCLE
Table 4
a. The t
RC,MIN
parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon how many column
accesses (each requiring t
CC
) are performed in each row access (t
RC
). The table lists the special cases (t
RC-R, 2tCC
, t
RC-W, 2tCC, noERAW
, t
RC-W 2tCC, ERAW
) in which two column accesses are per-
formed in each row access.
All other parameters are minimum.
b. t
PP-D
is the t
PP
parameter for precharges to different bank sets. See “Simultaneous Precharge” on page 57.
c. t
RR-D
is the t
RR
parameter for activates to different bank sets. See “Simultaneous Activation” on page 56.
d. See “Propagation Delay” on page 28.
e. t
Δ
WR-D
is the t
Δ
WR
parameter for write-read accesses to different bank sets. See “Multiple Bank Sets and the ERAW Feature” on page 54. Also, note that the value of t
Δ
WR-D
may not take on
the values {3,5,7} within the range{t
Δ
WR-D,MIN
, ... t
Δ
WR,MIN
-1}. t
Δ
WR-D
may assume any value
≥
t
Δ
WR,MIN
.
f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,ROWP-LRR2}
ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,ROWP-REFP}
Table 17
Timing Parameters (Continued)
Symbol
Parameter and Other Conditions
Min
(A)
Min
(B)
Min
(C)
Min
(D)
Units
Figure(s)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
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