參數(shù)資料
型號(hào)： EDX5116ADSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits XDR⑩ DRAM
中文描述： 512M比特的XDR DRAM的⑩
文件頁數(shù)： 30/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE
Data Sheet E1033E30 (Ver. 3.0)
30
EDX5116ADSE
As a result of these propagation delays, the position of packets
will have timing skews that depend upon whether they are
measured at the pins of the memory controller or the pins of
the memory component. For example, the CFM/CFMN sig-
nals at the pins of the memory component are t
PD-RQ
later
than at the pins of the memory controller. This is shown by the
cycle numbering of the CFM/CFMN signals at the two loca-
tions
—
in this example cycle T
1
at the memory controller
aligns with cycle T
0
at the memory component.
All the request packets on the RQ wires will have a t
PD-RQ
skew at the memory component relative to the memory con-
troller in this example. Because the t
PD-D
propagation delay of
write data matches the t
PD-RQ
propagation delay of the write
command, the controller may issue the write data packet D(a0)
relative to the COL packet with the first write command “WR
a0” with the normal write data delay t
CWD
. If the propagation
delays between the memory controller and memory compo-
nent were different for the RQ and DQ buses (not shown in
this example), the write data delay at the memory controller
would need to be adjusted.
A propagation delay is seen by the read command — that is,
the read command will be delayed by a t
PD-RQ
skew at the
memory component relative to the memory controller. The
memory component will return the read data packet Q(b0) rel-
ative to this read command with the normal read data delay
t
CAC
(at the pins of the memory component).
The read data packet will be skewed by an additional propaga-
tion delay of t
PD-Q
as it travels from the memory component
back to the memory controller. The effective read data delay
measured between the read command and the read data at the
memory controller will be t
CAC
+t
PD-RQ
+t
PD-Q
.
The t
PD-RQ
factor is caused by the propagation delay of the
request packets as they travel from memory controller to mem-
ory component. The t
PD-Q
factor is caused by the propagation
delay of the read data packets as they travel from memory com-
ponent to memory controller.
All timing parameters will be equal to their minimum values
except t
WR-BUB,XDRDRAM
(as in the top diagram), and the tim-
ing parameters t
RW-BUB,XDRDRAM
and t
Δ
RW
. These will be
larger than their minimum values by the amount (t
PD,CYC
-
t
PD,CYC,MIN
), where t
PD,CYC
= t
PD-D
+t
PD-Q
. This may be seen
by evaluating the two timing paths between cycle T
9
at the
Controller and cycle T
21
at the XDR DRAM:
t
Δ
RW
+ t
PD-RQ
+ t
CWD
=
t
PD-RQ
+ t
CAC
+ t
CC
+ t
RW-BUB,XDRDRAM
or
t
Δ
RW
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM
The following relationship was shown for Figure 12
t
Δ
RW ,MIN
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM,MIN
or
(t
Δ
RW
- t
Δ
RW ,MIN
)=
(t
RW-BUB,XDRDRAM
- t
RWBUB,XDRDRAM,MIN
)
In other words, the two timing parameters t
RW-BUB,XDRDRAM
and t
Δ
RW
will change together. The relationship of this change
to the propagation delay t
PD,CYC
(= t
PD-D
+t
PD-Q
) can be
derived by looking at the two timing paths from T15 to T21 at
the XDR DRAM:
t
PD-Q
+ t
CC
+ t
RW-BUB,XIO
+ t
PD-D
=
t
CC
+ t
RW-BUB,XDRDRAM
or
t
RW-BUB,XDRDRAM
= t
RW-BUB,XIO
+ t
PD-D
+ t
PD-Q
or
t
RW-BUB,XDRDRAM
= t
RW-BUB,XIO
+ t
PD,CYC
in a system with minimum propagation delays:
t
RW-BUB,XDRDRAM,MIN
= t
RW-BUB,XIO
+ t
PD,CYC,MIN
and since t
RW-BUB,XIO
is equal to t
RW-BUB,XIO,MIN
in both
cases, the following is true:
(t
PD,CYC
- t
PD,CYC,MIN
) =
(t
RW-BUB,XDRDRAM
- t
RW-BUB,XDRDRAM,MIN
) =
(t
Δ
RW
- t
Δ
RW ,MIN
)=
In other words, the values of the t
RW-BUB,XDRDRAM,MIN
and
t
Δ
RW ,MIN
timing parameters correspond to the value of
t
PD,CYC,MIN
for the system (this is equal to one t
CYCLE
). As
t
PD,CYC
is increased from this minimum value, t
RW-
BUB,XDRDRAM
and t
Δ
RW
increase from their minimum values
by an equivalent amount.
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