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參數(shù)資料
| 型號(hào)： | EDX5116ADSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 512M比特的XDR DRAM的⑩ |
| 文件頁數(shù)： | 46/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE |
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Data Sheet E1033E30 (Ver. 3.0)
46
EDX5116ADSE
Initialization
Figure 37 shows the topology of the serial interface signals of a
XDR DRAM system. The three signals RST, CMD, and SCK
are transmitted by the controller and are received by each XDR
DRAM device along the bus. The signals are terminated to the
VTERM supply through termination components at the end
farthest from the controller. The SDI input of the XDR
DRAM device furthest from the controller is also terminated
to VTERM. The SDO output of each XDR DRAM device is
transmitted to the SDI input of the next XDR DRAM device
(in the direction of the controller). This SDO/SDI daisy-chain
topology continues to the controller, where it ends at the SRD
input of the controller. All the serial interface signals are low-
true. All the signals use RSL signaling circuits, except for the
SDO output which uses CMOS signaling circuits.
Figure 37
S erial Interfac e S ystem Topology
Figure 38 shows the initialization timing of the serial interface
for the XDR DRAM[k] device in the system shown above.
Prior to initialization, the RST is held at zero. The CMD input
is not used here, and should also be held at zero. Note that the
inputs are all sampled by the negative edge of the SCK clock
input. The SDI input for the XDR DRAM[0] device is zero,
and is unknown for the remaining devices.
On negative SCK edge S
8
the RST input is sampled one. It is
sampled one on the next four edges, and is sampled zero on
edge S
12
a time t
RST-10
after it was first sampled one. The state
of the control registers in the XDR DRAM device are set to
their reset values after the first edge (S
8
) in which RST is sam-
pled one.
Figure 38
Initialization T iming for X DR DRAM[k] Device
The SDI inputs will be sampled one within a time t
RST-SDO,11
after RST is first sampled one in all the XDR DRAMs except
for XDR DRAM[0]. XDR DRAM[0]’s SDI input will always
be sampled zero.
XDR DRAM[k] will see its RST input sampled zero at S
12
, and
will then see its SDI input sampled zero at S
16
(after SDI had
XDR DRAM
RST CMD SCK
SDO
SDI
XDR DRAM
RST CMD SCK
SDO
SDI
XDR DRAM
RST CMD SCK
SDO
SDI
Controller
RST CMD SCK
SRD
...
...
VTERM
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
36
S
38
S
t
RST-SCK
Poweron
S
16
t
CYC,SCK
RST
SDI
(input)
SCK
CMD
SDO
(output)
‘0’
‘0’
= k * t
CYC,SCK
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
t
RST-SDI,00
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘x’
‘x’
‘x’
‘x’
‘1’
‘1’
t
RST-SDO,11
‘x’
‘1’
‘1’
‘1’
‘1’
‘1’
‘0’
‘0’
t
SDI-SDO,00
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘x’
‘x’
‘x’
‘x’
‘1’
‘1’
‘x’
‘1’
‘1’
‘1’
‘1’
‘1’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
t
RST-10
t
COREINIT
0
1
0
1
0
1
0
1
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
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