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參數(shù)資料
| 型號(hào)： | EDX5116ADSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 512M比特的XDR DRAM的⑩ |
| 文件頁數(shù)： | 57/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE |
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Data Sheet E1033E30 (Ver. 3.0)
57
EDX5116ADSE
Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW and simultaneous activation. This feature is simulta-
neous precharge, and the timing of several cases is shown in
Figure 47.
The t
PP
parameter specifies the minimum spacing between
packets with precharge commands in XDR DRAMs with a sin-
gle bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The t
PP-D
parameter specifies
the minimum spacing between packets with precharge com-
mands to different bank sets in a XDR DRAM with multiple
bank sets.
In Figure 47, Case 4 shows an example when both t
PP
and t
PP-
D
must be at least 4*t
CYCLE
. In such a case, precharge com-
mands to different bank sets satisfy the same constraint as pre-
charge commands to the same bank set.
In Figure 47, Case 2 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 2*t
CYCLE
. In such a
case, a precharge command to one bank set may be inserted
between two precharge commands to a different bank set.
In Figure 47, Case 1 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 1*t
CYCLE
. As in the
previous case, a precharge command to one bank set may be
inserted between two precharge commands to a different bank
set. In this case, the middle precharge command does not have
to be symmetrically placed relative to the two outer precharge
commands.
In Figure 47, Case 0 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 0*t
CYCLE
. This
means that two precharge commands may be issued on the
same CFM clock edge. This is possible by using the delay
mechanism in one of the two commands. See “Dynamic
Request Scheduling” on page 20. It is also possible by taking
advantage of the fact that two independent precharge com-
mands may be encoded within a single ROWP packet. In the
example shown, the ROWP packet contains both a REFP
command and a PRE command. Both precharge commands
will be issued internally to different bank sets on the same
CFM clock edge.
Figure 47
S imultaneous Precharge
—
t
PP-D
Cases
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
PP-D
PRE
REFP
PRE
t
PP-D
Case 4: t
PP-D
= 4*t
CYCLE
REFP & PRE have same t
RR
t
PP
PRE
REFP
PRE
Case 2: t
PP-D
= 2*t
CYCLE
REFP fits between two PRE
t
PP-D
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Case 1: t
PP-D
= 1*t
CYCLE
REFP fits between two PRE
t
PP
PRE
REFP
PRE
Case 0: t
PP-D
= 0*t
CYCLE
REFP simultaneous with PRE
t
PP-D
t
PP
PRE
REFP
PRE
t
PP-D
set different from two PRE
note - REFP is directed to bank
set different from two PRE
note - REFP is directed to bank
set different from PRE at T
12
note - REFP is directed to bank
a
a) EDX5116ADSE does not support case0.
The minimum value of t
PP-D
is 1.
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相關(guān)代理商/技術(shù)參數(shù) |
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| EDX5116ADSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
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