參數(shù)資料
型號(hào): EDX5116ADSE
廠商: Elpida Memory, Inc.
英文描述: 512M bits XDR⑩ DRAM
中文描述: 512M比特的XDR DRAM的⑩
文件頁(yè)數(shù): 53/78頁(yè)
文件大?。?/td> 3311K
代理商: EDX5116ADSE
Data Sheet E1033E30 (Ver. 3.0)
53
EDX5116ADSE
is that the COLM packet includes a M[7:0] field that indicates
the reserved bit pattern (for the eight bits of each byte) that
indicates that the byte is not to be written. This requires that
the alignment of bytes within the data packet be defined, and
also that the bit numbering within each byte be defined (note
that this was not necessary for the unmasked WR command).
In the figure, bytes are contained within a single DQ/DQN
pin pair
this is necessary so the dynamic width feature can be
supported. Thus, each pin pair carries two bytes of each data
packet. Byte[0] is transferred earlier than byte[16+0], and bit
[0] of each byte (corresponding to M[0]) is transferred first, fol-
lowed by the remaining bits in succession).
Figure 42
Write-Masked (WRM) Transac tion Example
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CC
t
CWD
t
CYCLE
a1
WRM
a2
WRM
D(a2)
D(a1)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
DQ0
DQN0
DQ15
DQN15
.
.
t
CAC
a1
RD
Q(a1)
Byte [0]
Bit- and Byte-number-
ing convention for write
and read data packets.
Byte [15]
Byte [16+15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14]
[15]
DQ1
DQN1
Byte [1]
Byte [16+0]
Byte [16+1]
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