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參數(shù)資料
| 型號(hào)： | EDX5116ADSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 512M比特的XDR DRAM的⑩ |
| 文件頁數(shù)： | 4/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE |
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Data Sheet E1033E30 (Ver. 3.0)
4
EDX5116ADSE
Table of Contents
Overview .......................................................................1
Features ........................................................................1
Pin Configuration .........................................................1
Ordering Information................................................... 2
Part Number .................................................................2
General Description ......................................................3
Table of Contents .........................................................4
Pin Description .............................................................7
Block Diagram ..............................................................8
Request Packets ......................................................... 10
Request Packet Formats .................................................10
Request Field Encoding ..................................................12
Request Packet Interactions ...........................................14
Request Interaction Cases ..............................................15
Dynamic Request Scheduling ........................................20
Memory Operations ....................................................22
Write Transactions ..........................................................22
Read Transactions ...........................................................24
Interleaved Transactions .................................................26
Read/Write Interaction ..................................................28
Propagation Delay ...........................................................28
Register Operations ....................................................32
Serial Transactions ...........................................................32
Serial Write Transaction .................................................32
Serial Read Transaction ..................................................32
Register Summary ............................................................34
Maintenance Operations ............................................40
Refresh Transactions .......................................................40
Interleaved Refresh Transactions ..................................40
Calibration Transactions .................................................42
Power State Management ...............................................44
Initialization ......................................................................46
XDR DRAM Initialization Overview ..........................47
XDR DRAM Pattern Load with WDSL Reg .............48
Special Feature Description ....................................... 50
Dynamic Width Control .................................................50
Write Masking ..................................................................52
Multiple Bank Sets and the ERAW Feature ................54
Simultaneous Activation .................................................56
Simultaneous Precharge .................................................57
Operating Conditions ................................................ 58
Electrical Conditions .......................................................58
Timing Conditions ..........................................................59
Operating Characteristics .......................................... 60
Electrical Characteristics ................................................60
Supply Current Profile ....................................................61
Timing Characteristics ....................................................62
Timing Parameters ..........................................................62
Receive/Transmit Timing ......................................... 64
Clocking ............................................................................64
RSL RQ Receive Timing ................................................65
DRSL DQ Receive Timing ............................................66
DRSL DQ Transmit Timing .........................................68
Serial Interface Receive Timing .....................................70
Serial Interface Transmit Timing ..................................71
Package Description .................................................. 72
Package Parasitic Summary ............................................72
Package Drawing ............................................................74
Package Pin Numbering .................................................75
Recommended Soldering Conditions ....................... 76
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
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