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參數(shù)資料
| 型號： | EDX5116ADSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 512M比特的XDR DRAM的⑩ |
| 文件頁數(shù)： | 54/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE |
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Data Sheet E1033E30 (Ver. 3.0)
54
EDX5116ADSE
Multiple Bank Sets and the ERAW Feature
Figure 45 shows a block diagram of a XDR DRAM in which
the banks are divided into two sets (called the even bank set
and the odd bank set) according to the least-significant bit of
the bank address field. This XDR DRAM supports a feature
called “Early Read After Write” (hereafter called “ERAW”).
The logic that accepts commands on the RQ11..0 signals is
capable of operating these two bank sets independently. In
addition, each bank set connects to its own internal “S” data
bus (called S0 and S1). The receive interface is able to drive
write data onto either of these internal data buses, and the
transmit interface is able to sample read data from either of
these internal data buses. These capabilities will permit the
delay between a write column operation and a read column
operation to be reduced, thereby improving performance.
Figure 43 shows the timing previously presented in Figure 12,
but with the activity on the internal S data bus included. The
write-to-read parameter t
Δ
WR
ensures that there is adequate
turnaround time on the S bus between D(a2) and Q(c1).
When ERAW is supported with odd and even bank sets, the
t
Δ
WR,MIN
parameter must be obeyed when the write and read
column operations are to the same bank set, but a second
parameter t
Δ
WR-D
permits earlier column operations to the
opposite bank set. Figure 44 shows how this is possible
because there are two internal data buses S0 and S1. In this
example, the four column read operations are made to the
same bank Bb, but they could use different banks as long as
they all belonged to the bank set that was different from the
bank set containing Ba (for the column write operations).
Figure 43
Write/Read Interac tion
—
No ERAW Feature
Figure 44
Write/Read Interac tion
—
ERAW Feature
T
0
T
1
T
2
T
3
CFM
CFMN
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
Transaction c: RD
a1 = {Ba,Ca1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
c2 = {Bc,Cc2}
c2
RD
t
CWD
Q(c2)
Q(c1)
t
CAC
a1
WR
D(a2)
D(a1)
t
CYCLE
c1
RD
a2
WR
t
Δ
WR
DQ15..0
DQN15..0
t
CC
t
WR-BUB,XDRDRAM
turnaround
S[15:0]
[15:0]
t
CC
D(a1)
D(a2)
Q(c1)
Q(c2)
T
0
T
1
T
2
T
3
CFM
CFMN
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1 = {Ba,Ca1}
b1 = {Bb,Cb1}
c1 = {Bc,Cc1}
a2 = {Ba,Ca2}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
c1
RD
t
CWD
Q(c1)
Q(b4)
t
CAC
t
Δ
WR-D
a1
D(a2)
D(a1)
t
CYCLE
b4
RD
a2
WR
DQ15..0
DQN15..0
t
CC
S0[15:0]
[15:0]
t
CC
D(a1)
D(a2)
Q(b4)
Q(c1)
S1[15:0]
[15:0]
Q(b1)
Q(b2)
b1
RD
b3
RD
b2
RD
Q(b2)
Q(b1)
Q(b3)
Q(b3)
t
WR-BUB,XDRDRAM
turnaround
Bb is in different bank set than Ba
Bc is in same bank set as Ba
Bank Restrictions
b4 = {Bb,Cb4}
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相關代理商/技術參數(shù) |
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|---|---|
| EDX5116ADSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
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