參數(shù)資料
型號(hào)： EDX5116ADSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits XDR⑩ DRAM
中文描述： 512M比特的XDR DRAM的⑩
文件頁數(shù)： 10/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE
Data Sheet E1033E30 (Ver. 3.0)
10
EDX5116ADSE
Request Packets
A
request packet
carries address and control information to
the memory device. This section contains tables and diagrams
for packet formats, field encodings and packet interactions.
Request Packet Formats
There are five types of request packets:
1.
ROWA
—
specifies an ACT command
2.
COL
—
specifies RD and WR commands
3.
COLM
—
specifies a WRM command
4.
ROWP
—
specifies PRE and REF commands
5.
COLX
—
specifies the remaining commands
Table 2 describes fields within different request packet types.
Various request packet type formats are illustrated in Figure 3.
Each packet type consists of 24 bits sampled on the RQ11..0
pins on two successive edges of the CFM/CFMN clock. The
request packet formats are distinguished by the OP3..0 field.
This field also specifies the operation code of the desired com-
mand.
In the ROWA packet, a bank address (BA), row address (R),
and command delay (DELA) are specified for the activate
(ACT) command.
In the COL packet, a bank address (BC), column address (C),
sub-column address (SC), command delay (DELC), and sub-
opcode (WRX) are specified for the read (RD) and write (WR)
commands.
In the COLM packet, a bank address (BC), column address
(C), sub-column address (SC), and mask field (M) are specified
for the masked write (WRM) command.
In the ROWP packet, two independent commands may be
specified. A bank address (BP) and sub-opcode (POP) are
specified for the precharge (PRE) commands. An address field
(RA) and sub-opcode (ROP) are specified for the refresh
(REF) commands.
In the COLX packet, a sub-operation code field (XOP) is spec-
ified for the remaining commands.
Table 2
Request Field Description
Field
Packet Types
Description
OP3..0
ROWA/ROWP/COL/COLM/COLX
4-bit operation code that specifies packet format.
(Encoded commands are in Table 3 on page 12).
DELA
ROWA
Delay the associated row activate command by 0 or 1 t
CYCLE
.
BA2..0
ROWA
3-bit bank address for row activate command.
R11..0
ROWA
12-bit row address for row activate command.
WRX
COL
Specifies RD (=0) or WR (=1) command.
DELC
COL
Delay the column read or write command by 0 or 1 t
CYCLE
.
BC2..0
COL/COLM
3-bit bank address for column read or write command.
C9..4
COL/COLM
6-bit column address for column read or write command.
SC3..0
COL/COLM
4-bit sub-column address for dynamic width (see “Dynamic Width Control” on page 50).
M7..0
COLM
8-bit mask for masked-write command WRM.
POP2..0
ROWP
3-bit operation code that specifies row precharge command with a delay of 0 to 3 t
CYCLE
.
(Encoded commands are in Table 5 on page 13).
BP2..0
ROWP
3-bit bank address for row precharge command.
ROP2..0
ROWP
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 4 on page 12).
RA7..0
ROWP
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value
XOP3..0
COLX
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 6 on page 13).
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