參數(shù)資料
型號： EDX5116ADSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits XDR⑩ DRAM
中文描述： 512M比特的XDR DRAM的⑩
文件頁數(shù)： 58/78頁
文件大小： 3311K
代理商： EDX5116ADSE
Data Sheet E1033E30 (Ver. 3.0)
58
EDX5116ADSE
Operating Conditions
Electrical Conditions
Table 12 summarizes all electrical conditions (temperature and
voltage conditions) that may be applied to the memory compo-
nent. The first section of parameters is concerned with abso-
lute voltages, storage, and operating temperatures, and the
power supply, reference, and termination voltages.
The second section of parameters determines the input voltage
levels for the RSL RQ signals. The high and low voltages must
satisfy a symmetry parameter with respect to the
V
REF,RSL
.
The third section of parameters determines the input voltage
levels for the RSL SI (serial interface) signals. The high and low
voltages must satisfy a symmetry parameter with respect to the
V
REF,RSL
.
The fourth section of parameters determines the input voltage
levels for the CFM clock signals. The high and low voltages are
specified by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage
levels for the write data signals on the DRSL DQ pins. The
high and low voltage are specified by a common-mode value
and a swing value.
Table 12
Electrical Conditions
Symbol
Parameter
Minimum
Maximum
Unit
V
IN,ABS
Voltage applied to any pin (except VDD) with respect to GND
- 0.300
1.500
V
V
DD,ABS
Voltage on VDD with respect to GND
- 0.500
2.300
V
T
STORE
Storage temperature
- 50
100
°
C
T
J
Junction temperature under bias during normal operation
0
100
°
C
V
DD
Supply voltage applied to VDD pins during normal operation
1.800 - 0.090
1.800 + 0.090
V
V
REF,RSL
RSL - Reference voltage applied to VREF pin
a
V
TERM,RSL
- 0.450 - 0.025
V
TERM,RSL
- 0.450 + 0.025
V
V
TERM,DRSL
DRSL - Termination voltage applied to VTERM pins
1.200 - 0.060
1.200 + 0.060
V
V
IL,RQ
RSL RQ inputs -low voltage
V
REF,RSL
- 0.450
V
REF,RSL
- 0.150
V
V
IH,RQb
RSL RQ inputs -high voltage
V
REF,RSL
+ 0.150
V
REF,RSL
+ 0.450
V
R
A,RQ
RSL RQ inputs - data asymmetry:
R
A,RQ
= (V
IH,RQ
-V
REF,RSL
)/(V
REF,RSL
-V
IL,RQ
)
0.8
1.2
-
V
IL,SI
RSL Serial Interface inputs -low voltage
V
REF,RSL
- 0.450
V
REF,RSL
- 0.200
V
V
IH,SIb
RSL Serial Interface inputs -high voltage
V
REF,RSL
+ 0.200
V
REF,RSL
+ 0.450
V
R
A,SI
RSL Serial Interface inputs - data asymmetry:
R
A,SI
= (V
IH,SI
-V
REF,RSL
)/(V
REF,RSL
-V
IL,SI
)
0.8
1.2
-
V
ICM,CFM
CFM/CFMN input - common mode
V
TERM,DRSL
-
V
ISW,CFM
/2 - 0.020
V
TERM,DRSL
-
V
ISW,CFM
/2 + 0.020
V
V
ISW,CFM
CFM/CFMN input - high-low swing: V
ISW,CFM
= (V
IH,CFMb
- V
IL,CFM
)
0.150
0.300
V
V
ICM,DQ
DRSL DQ inputs - common mode
V
TERM,DRSL
-
V
ISW,DQ/
2 - 0.020
V
TERM,DRSL
-
V
ISW,DQ/
2 + 0.020
V
V
ISW,DQ
DRSL DQ inputs - high-low swing: V
ISW,DQ
= (V
IH,DQb
- V
IL,DQ
)
0.050
0.300
V
a. V
TERM,RSL
is typically 1.200V±0.060V. It connects to the RSL termination components, not to this DRAM component.
b. V
IH
is typically equal to V
TERM,RSL
or V
TERM,DRSL
(whichever is appropriate) under DC conditions in a system.
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