參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 95/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： 定時卡 IC，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
72
Register Name:
MCR6
Register Description:
Master Configuration Register 6
Register Address:
38h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2AF
DIG2SS
DIG1SS
—
Default
0
see below
1
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies.
0 = Digital2 N x E1 or N x DS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or N x 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whether the clock rates generated by the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET compatible) or multiples of 2.048MHz (SDH
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the MCR7 register. When
RST = 0 the default value of this bit is latched from the SONSDH pin.
DIG2AF = 0:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
DIG2AF = 1:
6.312MHz, 10MHz, or N x 19.44MHz
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whether the clock rates generated by the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatible). The specific multiple is set in the DIG1F field of the MCR7 register. When
RST = 0 the default value of
this bit is latched from the SONSDH pin.
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
Register Name:
MCR7
Register Description:
Master Configuration Register 7
Register Address:
39h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2F[1:0]
DIG1F[1:0]
—
Default
0
1
0
Bits 7 and 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the
frequency of the Digital2 clock synthesizer.
DIG2AF = 0
DIG2AF = 1
DIG2SS = 1
DIG2SS = 0
DIG2SS = 1
DIG2SS = 0
00 = 1544kHz
00 = 2048kHz
00 = 19.44MHz
00 = 6.312MHz
01 = 3088kHz
01 = 4096kHz
01 = 38.88MHz
01 = undefined
10 = 6176kHz
10 = 8192kHz
10 = undefined
10 = 10MHz
11 = 12,352kHz
11 = 16,384kHz
11 = undefined
Bits 5 and 4: Digital1 Frequency (DIG1F[1:0]). This field and MCR6:DIG1SS configure the frequency of the
Digital1 clock synthesizer.
DIG1SS = 1
DIG1SS = 0
00 = 1544kHz
00 = 2048kHz
01 = 3088kHz
01 = 4096kHz
10 = 6176kHz
10 = 8192kHz
11 = 12,352kHz
11 = 16,384kHz
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