參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 89/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
67
DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode)
0000 = 10MHz (internally divided down to 5MHz)
0001 = 25MHz (internally divided down to 5MHz)
0010 = 62.5MHz (internally down to 31.25MHz)
0011 = 125MHz (internally down to 31.25MHz)
0100 = 156.25MHz (differential inputs only; internally divided down to 31.25MHz)
0101–1111 = undefined
FREQ[3:0] Default Values:
ICR3–ICR4: 0000b
ICR5–ICR7, ICR9: 0011b
Register Name:
VALCR1
Register Description:
Input Clock Valid Control Register 1
Register Address:
30h
Bit #
7
6
5
4
3
2
1
0
Name
IC6
IC5
IC4
IC3
Default
1
0
1
0
Bits 5 to 2: Input Clock Valid Control (IC[6:3]). These control bits can be used to force input clocks to be
considered invalid. If a clock is invalidated by one of these control bits it will not appear in the priority table in the
PTAB1 and PTAB2 registers, even if the clock is otherwise valid. These bits are useful when system software
needs to force clocks to be invalid in response to OAM commands. Note that setting a VALCR bit low has no effect
on the corresponding bit in the VALSR registers. See Sections 7.6.2.
0 = Force invalid
1 = Do not force invalid; determine validity normally
Register Name:
VALCR2
Register Description:
Input Clock Valid Control Register 2
Register Address:
31h
Bit #
7
6
5
4
3
2
1
0
Name
IC9
Default
0
1
Bit 0: Input Clock Valid Control (IC9). This bit has the same behavior as the bits in VALCR1 but for the IC9 input
clock.
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