參數(shù)資料
型號(hào): DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 113/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
89
Register Name:
T0ABW
Register Description:
T0 DPLL Acquisition Bandwidth Register
Register Address:
69h
Bit #
7
6
5
4
3
2
1
0
Name
0
RSV1
RSV2
T0ABW[2:0]
Default
0
1
Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). These bits are reserved for future use, and can be written to and
read back.
Bits 2 to 0: T0 DPLL Acquisition Bandwidth (T0ABW[2:0]). This field configures the bandwidth of the T0 DPLL
when acquiring lock. When AUTOBW = 0 in the MCR9 register, the T0LBW bandwidth is used for acquisition and
for locked operation. When AUTOBW = 1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth is
used for locked operation. See Section 7.7.3.
111 = 18Hz (default)
000 = 35Hz
001 = 70Hz
010 = {unused value, undefined}
011 = 18Hz
100 = 120Hz
101 = 250Hz
110 = 400Hz
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