參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 39/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
21
LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and
direct-lock mode is used.
7.4.2.4 DIVN Mode
In DIVN mode, an internal divider is configured from the value stored in the DIVN registers. The DIVN value must
be chosen so that when the selected reference is divided by DIVN+1, the resulting clock frequency is the same as
the standard direct lock frequency selected in the FREQ field of the ICR register. The DPLL locks to the output of
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52MHz. The
DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks
configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as
155.52MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125MHz.
7.5
Input Clock Monitoring
Each input clock is continuously monitored for activity. Activity monitoring is described in Sections 7.5.2 and 7.5.3.
The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers VALSR1
or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers
MSR1 or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers IER1 or
IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL.
7.5.1 Frequency Monitoring
The DS3105 monitors the frequency of each input clock and invalidates any clock whose frequency is more than
10,000ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit. The
frequency range measurement uses the internal 204.8MHz master clock as the frequency reference.
7.5.2 Activity Monitoring
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket
accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and
gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully
between events and no alarm is declared. When events occur close enough together, the accumulator increments
faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events
occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the
alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.
The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 to 3) in the
BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare
threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers.
Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in
which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz, 156.25MHz,
125MHz, 62.5MHz, 25MHz and 10MHz input clocks). Thus, the “fill” rate of the bucket is at most 1 unit per 128ms,
or approximately 8 units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator
decrements if no irregularities occur. Thus the “l(fā)eak” rate of the bucket is approximately 8, 4, 2, or 1 units/second.
A leak is prevented when a fill event occurs in the same interval.
When the value of an accumulator reaches the alarm threshold (LBxU register), the corresponding ACT alarm bit is
set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an
accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock’s
ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay
rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration
registers must have the following relationship at all times: LBxS
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