- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1994 > DS3105LN+ (Maxim Integrated Products)IC TIMING LINE CARD 64-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 46/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)
DS3105
28
7.7.1.3 Locked State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). In the locked state
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding
ACT bit set in the ISR register), the selected reference is invalidated (ICn bit goes low in VALSR registers), and the
state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or,
after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
If loss-of-lock (see Section 7.7.6) is declared while in the locked state, the state machine transitions to the loss-of-
lock state.
7.7.1.4 Loss-of-Lock State
When the loss-of-lock detectors (see Section 7.7.6) indicate loss-of-phase lock, the state machine immediately
transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds
(default value of PHLKTO register) to regain phase lock. If phase lock is regained during that period for more than
2 seconds, the state machine transitions back to the locked state.
If, during the phase-lock timeout period specified by PHLKTO, the selected reference is so impaired that an activity
alarm is raised (corresponding ACT bit set in the ISR registers), the selected reference is invalidated (ICn bit goes
low in VALSR registers), and after being invalid for 2 seconds the state machine transitions to either the prelocked
2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid).
If phase lock cannot be regained by the end of the phase-lock timeout period, a phase-lock alarm is raised
(corresponding LOCK bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR
registers), and the state machine transitions to either the prelocked 2 state (if another valid input clock is available)
or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
7.7.1.5 Prelocked 2 State
The prelocked and prelocked 2 states are similar. The prelocked 2 state provides a 100-second period (default
value of PHLKTO register) for the DPLL to lock to the new selected reference. If phase lock (see Section 7.7.6) is
achieved for more than 2 seconds during this period, the state machine transitions to locked mode.
If the DPLL fails to lock to the new selected reference within the phase-lock timeout period specified by PHLKTO, a
phase-lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit goes
low in VALSR registers). If another input clock is valid, the state machine re-enters the prelocked 2 state and tries
to lock to the alternate input clock. If no other input clocks are valid for 2 seconds, the state machine transitions to
the holdover state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period, the state machine re-enters the prelocked 2 state and tries to lock to the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, the PHLKTO register must be
configured accordingly.
7.7.1.6 Holdover State
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no
other valid input clocks available. During holdover the T0 DPLL is not phase-locked to any input clock but instead
generates its output frequency from stored frequency information acquired while it was in the locked state. When at
least one input clock has been declared valid, the state machine immediately transitions from holdover to the
prelocked 2 state, and tries to lock to the highest priority valid clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3106LN+ | IC TIMING LINE CARD 64-LQFP |
| DS3231MZ+ | IC RTC I2C 8SOIC |
| DS3231SN#T&R | IC RTC W/TCXO 16-SOIC |
| DS3232MZ+ | IC RTC W/SRAM I2C 8SOIC |
| DS3232SN#T&R | IC RTC W/TCXO 20-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。