參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 45/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
27
Figure 7-2. T0 DPLL State Transition Diagram
Free-Run
select ref
(001)
Prelocked
wait for ≤ 100s
(110)
Reset
all input clocks evaluated
at least one input valid
(selected reference invalid > 2s
OR out of lock >100s)
AND no valid input clock
Locked
(100)
phase-locked to
selected reference > 2s
Loss-of-Lock
wait for ≤ 100s
(111)
Holdover
select ref
(010)
loss-of-lock on
selected reference
phase-lock regained
on selected reference
within 100s
Prelocked 2
wait for ≤ 100s
(101)
(selected reference invalid > 2s
OR out of lock > 100s) AND
no valid input clock available
[selected reference invalid OR
(revertive mode AND valid higher priority input)
OR out of lock > 100s] AND
valid input clock available
[selected reference invalid OR
out of lock > 100s OR
(revertive mode AND valid higher priority input)]
AND valid input clock available
[selected reference invalid OR
out of lock >100s OR
(revertive mode AND valid higher priority input)]
AND valid input clock available
(selected reference invalid > 2s
OR out of lock >100s) AND
no valid input clock available
all input clocks evaluated
at least one input valid
selected reference invalid > 2s
AND
no valid input clock available
[selected reference invalid OR
(revertive mode AND valid higher priority input)]
AND valid input clock available
phase-locked
to selected
reference > 2s
Note 1:
An input clock is valid when it has no activity alarm and no phase-lock alarm (see the VALSR registers and the ISR registers).
Note 2:
All input clocks are continuously monitored for activity.
Note 3:
Only the selected reference is monitored for loss-of-lock.
Note 4:
Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
Note 5:
To simply the diagram, the phase-lock timeout period is always shown as 100s, which is the default value of the PHLKTO
register. Longer or shorter timeout periods can be specified as needed by writing the appropriate value to the PHLKTO register.
Note 6:
When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state.
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參數(shù)描述
DS3105LN+ 功能描述:計時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
DS3106 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC
DS3106A10SL3S(621) 制造商:Amphenol Corporation 功能描述:
DS3106A14S2S 制造商:Amphenol Corporation 功能描述:
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