參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 40/124頁
文件大小： 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： 定時卡 IC，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
22
When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the x
in LBxU is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in seconds is
2^LBxD
× (LBxS – LBxL) / 8. As an example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The
minimum time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm
would be 2^0
× (10 – 1) / 8 = 1.125 seconds.
7.5.3 Selected Reference Activity Monitoring
The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected
reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from
the reference until the reference is available again. By design, the regular input clock activity monitor (Section
7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz,
125MHz, 62.5MHz, 25MHz, and 10MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the
selected reference and sets the SRFAIL bit in MSR2. The setting of the SRFAIL bit can cause an interrupt request
if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin follows the state of the
SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see Section 7.6.4).
When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the
selected reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL
continues to track the selected reference using nearest edge locking (
±180°) to avoid cycle slips. When NALOL =
1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state machine to transition
to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if enabled. If the selected
reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL tracks the
selected reference using phase/frequency locking (
±360°) until phase lock is reestablished.
When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the
PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If
NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an
interrupt request if enabled.
7.6
Input Clock Priority, Selection, and Switching
7.6.1 Priority Configuration
During normal operation, the selected reference for the T0 DPLL is chosen automatically based on the priority
rankings assigned to the input clocks in the input priority registers (IPR2, IPR3, and IPR5). Each of these registers
has priority fields for one or two input clocks. When T4T0 = 0 in the MCR11 register, the IPR registers specify the
input clock priorities for the T0 DPLL. When T4T0 = 1, they have no meaning. The default input clock priorities are
shown in Table 7-3.
There is an inter-lock mechanism between IC3 and IC5 and between IC4 and IC6 so that only two of the inputs can
be automatically selected. When IPR2.PRI3 is written with a priority other than 0, IPR3.PRI5 is automatically set to
0. When IPR3.PRI5 is written with a priority other than 0, IPR2.PRI3 is automatically set to 0. When IPR2.PRI4 is
written with a priority other than 0, IPR3.PRI6 is automatically set to 0. When IPR3.PRI6 is written with a priority
other than 0, IPR2.PRI4 is automatically set to 0.
Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable
for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
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