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參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 36/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
19
The outputs of the T0 DPLL and the T4 DPLL can be connected to seven output DFS engines. See Figure 7-1.
Three of these output DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and
filter DPLL output jitter. The outputs of the APLLs are divided down to make a wide variety of possible frequencies
available at the output clock pins. The output frequencies from the T0 DPLL can be synchronized to an input 2, 4,
or 8kHz sync signal (SYNC1, SYNC2, or SYNC3 input pins).
The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency and
phase-locked to the T0 DPLL. The OC6 output is LVDS/LVPECL; the OC3 is CMOS. Altogether more than 60
output frequencies are possible, ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz, and the
MFSYNC output clock is always 2kHz.
7.2
Device Identification and Protection
The 16-bit read-only ID field in the ID1 and ID2 registers is set to 0C21h = 3105 decimal. The device revision can
be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The
register set can be protected from inadvertent writes using the PROT register.
7.3
Local Oscillator and Master Clock Configuration
The T0 DPLL, the T4 DPLL, and the output DFS engines operate from a 204.8MHz master clock. The master clock
is synthesized from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability
of the T0 DPLL in free-run or holdover is equivalent to the stability of the local oscillator. Selection of an appropriate
local oscillator is therefore of crucial importance if the telecom standards listed in Table 1-1 are to be met. Simple
XOs can be used in less stringent cases, but TCXOs or even OCXOs may be required in the most demanding
applications. Careful evaluation of the local oscillator component is necessary to ensure proper performance.
Contact Microsemi timing products technical support for recommended oscillators.
The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the
local oscillator clock. The MCLKFREQ field in registers MCLK1 and MCLK2 specifies the frequency adjustment to
be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps.
7.4
Input Clock Configuration
The DS3105 has five input clocks: IC3 to IC6 and IC9. Table 7-1 provides summary information about each clock,
including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks,
out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller.
7.4.1 Signal Format Configuration
Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects
the available frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz
frequency is available. When SONSDH = 0 (SDH mode), the 2.048MHz frequency is available. During reset the
default value of this bit is latched from the SONSDH pin.
Input clocks IC5 and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper
set of external components. The recommended LVDS termination is shown in Figure 10-1 while the recommended
LVPECL termination is shown in Figure 10-2. The electrical specifications for these inputs are listed in Table 10-4.
To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltage-divider to bias the
ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If a differential input is
not used it should be left unconnected (one input is internally pulled high and the other internally pulled low). (See
also MCR5:IC5SF and IC6SF.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
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