參數(shù)資料
型號(hào): DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 94/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
71
Register Name:
MCR4
Register Description:
Master Configuration Register 4
Register Address:
35h
Bit #
7
6
5
4
3
2
1
0
Name
T4FORCE[3:0]
Default
1
0
Bits 3 to 0: T4 DPL Force Selected Reference (T4FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T4 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). Since the T4 DPLL always operates in revertive mode, the
forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well.
When a reference is forced, the activity monitor for that input continues to operate and affect the relevant ISR,
VALSR, and MSR register bits. See Section 7.6.3.
0000 = Automatic source selection (normal operation)
0001 = {unused value, undefined}
0010 = {unused value, undefined}
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value, undefined}
1000 = {unused value, undefined}
1001 = Force to IC9
1010–1110 = {unused value, undefined}
1111 = Automatic source selection (normal operation)
Register Name:
MCR5
Register Description:
Master Configuration Register 5
Register Address:
36h
Bit #
7
6
5
4
3
2
1
0
Name
RSV4
RSV3
RSV2
RSV1
IC6SF
Default
0
Bits 7 to 4: Reserved Bit 4 to 1 (RSV[4:1]). These bits are reserved for future use, and can be written to and read
back.
Bit 1: Input Clock 6 Signal Format (IC6SF). For backward compatibility this bit can be written to and read back,
but it does not affect the IC6POS/NEG inputs pins. See Section 7.4.1.
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