參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 71/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
50
8.
Register Descriptions
The DS3105 has an overall address range from 000h to 1FFh. Table 8-1 in Section 8.4 shows the register map. In
each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved
and must be written with 0. Writing other values to these registers may put the device in a factory test mode
resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register
fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are read-
write. Register fields are described in detail in the register descriptions that follow Table 8-1.
Note: Systems must be able to access the entire address range from 0 to 01FFh. Proper device initialization
requires a sequence of writes to addresses in the range 0180-01FFh.
8.1
Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status
bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits.
ISR#.LOCK# are special-case latched status bits because they cannot create an interrupt request on the INTREQ
pin and a “write 0” is needed to clear them.
8.2
Configuration Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—” are reserved and must be written with 0.
8.3
Multiregister Fields
Multiregister fields—such as FREQ[18:0] in registers FREQ1, FREQ2, and FREQ3—must be handled carefully to
ensure that the bytes of the field remain consistent. A write access to a multiregister field is accomplished by
writing all the registers of the field in any order, with no other accesses to the device in between. If the write
sequence is interrupted by another access, none of the bytes are written and the MSR4:MRAA latched status bit is
set to indicate the write was aborted. A read access from a multiregister field is accomplished by reading the
registers of the field in any order, with no other accesses to the device in between. When one register of a
multiregister field is read, the other register(s) in the field are frozen until after they are all read. If the read
sequence is interrupted by another access, the registers of the multibyte field are unfrozen and the MSR4:MRAA
bit is set to indicate the read was aborted. For best results, interrupt servicing should be disabled in the
microprocessor before a multiregister access and then enabled again after the access is complete. The
multiregister fields are:
FIELD
REGISTERS
ADDRESSES
TYPE
FREQ[18:0]
0Ch, 0Dh, 07h
Read Only
MCLKFREQ[15:0]
3Ch, 3Dh
Read/Write
HARDLIM[9:0]
41h, 42h
Read/Write
DIVN[15:0]
46h, 47h
Read/Write
OFFSET[15:0]
70h, 71h
Read/Write
PHASE[15:0]
77h, 78h
Read Only
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