參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 78/124頁
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
57
Register Name:
MSR3
Register Description:
Master Status Register 3
Register Address:
08h
Bit #
7
6
5
4
3
2
1
0
Name
FSMON
T4LOCK
Default
0
1
0
1
0
Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON
transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt
request on the INTREQ pin if the FSMON interrupt enable bit is set in the IER3 register. See Section 7.9.
Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock status of the T4
DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when
previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes
again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit
is set in the IER3 register. See Section 7.7.6.
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