TABLE OF CONTENTS (Continued)
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ColdFire2/2M User’s Manual
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MOTOROLA
2.6.1.1
2.6.1.2
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.1.9
2.6.1.10
2.6.1.11
2.6.1.12
2.6.1.13
2.6.1.14
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.2.4
2.6.2.5
2.6.2.6
2.6.2.7
2.6.2.8
2.6.2.9
2.6.2.10
2.6.2.11
2.6.2.12
2.6.2.13
Test Address Bus (TEST_ADDR[14:2]) ..........................................2-13
Test Control (TEST_CTRL).............................................................2-13
Test IDATA Read (TEST_IDATA_RD)............................................2-13
Test IDATA Write (TEST_IDATA_WRT) .........................................2-13
Test Instruction Cache Read Hit (TEST_RHIT)...............................2-13
Test Invalidate Inhibit (TEST_IVLD_INH)........................................2-13
Test ITAG Write (TEST_ITAG_WRT)..............................................2-13
Test KTA Mode Enable (TEST_KTA)..............................................2-13
Test Mode Enable (TEST_MODE)..................................................2-13
Test SRAM Read (TEST_SRAM_RD) ............................................2-13
Test SRAM Write (TEST_SRAM_WRT)..........................................2-13
Test Read (TEST_RD)....................................................................2-13
Test ROM Read (TEST_ROM_RD) ................................................2-13
Test Write Inhibit (TEST_WR_INH).................................................2-13
Scan Signal Description.......................................................................2-13
Scan Enable (SCAN_ENABLE).......................................................2-14
Scan Exercise Array (SCAN_XARRAY)..........................................2-14
Scan Input (SCAN_IN[15:0]) ...........................................................2-14
Scan Mode (SCAN_MODE)............................................................2-14
Scan Output (SCAN_OUT[15:0]).....................................................2-14
Scan Test Ring Clock (TR_CLK).....................................................2-14
Scan Test Ring Core Mode Enable (TR_CORE_EN) .....................2-14
Scan Test Ring Data Input 0 (TR_DI0)............................................2-14
Scan Test Ring Data Input 1 (TR_DI1)............................................2-14
Scan Test Ring Data Output 0 (TR_DO0).......................................2-14
Scan Test Ring Data Output 1 (TR_DO1).......................................2-14
Scan Test Ring Enable (TR_EN).....................................................2-14
Scan Test Ring Mode (TR_MODE).................................................2-14
Section 3
Master Bus Operation
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Signal Description........................................................................................3-1
68K Interrupt Acknowledge Mode Enable (IACK_68K)..........................3-1
Master Address Bus (MADDR[31:0]) .....................................................3-1
Master Arbiter Control (MARBC[1:0]).....................................................3-1
Master Freeze (MFRZB) ........................................................................3-2
Master Kill (MKILLB) ..............................................................................3-2
Master Read Data Bus (MRDATA[31:0]) ...............................................3-2
Master Read Data Input Enable (MIE)...................................................3-2
Master Read/Write (MRWB)...................................................................3-2
Master Reset (MRSTB)..........................................................................3-2
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Freescale Semiconductor, Inc.
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