
LIST OF TABLES (Continued)
Figure
Number
Page
Number
Title
xxiv
ColdFire2/2M User’s Manual
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MOTOROLA
5-8
5-9
5-10
6-1
6-2
6-3
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
A-1
Valid SRAM Address Bits ...............................................................................5-15
SRAM Configuration Encoding.......................................................................5-16
Valid SRAM Base Address Bits......................................................................5-17
Mask Addressing Mode ....................................................................................6-4
Accumulator Result in Saturation Mode............................................................6-5
MAC Instruction Set Summary..........................................................................6-6
Processor Status Encoding ..............................................................................7-2
CPU-Generated Message Encoding ................................................................7-9
BDM Command Summary..............................................................................7-10
BDM Size Field Encoding...............................................................................7-11
Control Register Map......................................................................................7-22
Definition of DRc Encoding - Read.................................................................7-24
Definition of DRc Encoding - Write .................................................................7-25
DDATA, CSR[31:28] Breakpoint Response....................................................7-26
Shared BDM/Breakpoint Hardware.................................................................7-28
Misaligned Data Operand References............................................................7-34
BDM Connector Correlation............................................................................7-40
Misaligned Operand References ......................................................................9-2
Move Byte and Word Execution Times.............................................................9-3
Move Long Execution Times ............................................................................9-3
One Operand Instruction Execution Times.......................................................9-4
Two Operand Instruction Execution Times.......................................................9-5
Miscellaneous Instruction Execution Times......................................................9-7
MAC Instruction Execution Times.....................................................................9-8
General Branch Instruction Execution Times....................................................9-8
BRA,
BCC
Instruction Execution Times............................................................9-8
Register Summary............................................................................................A-1
F
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