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| 型號(hào)： | COLDFIRE3UM |
| 英文描述： | Version 3 ColdFire Core User＇s Manual |
| 中文描述： | 版本3 ColdFire內(nèi)核的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 102/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE3UM |
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Exception Processing
MOTOROLA
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
4-9
The ColdFire2/2M has a misalignment unit which will generate a series of aligned bus cycles
to access data requested from a misaligned address. As a result, misaligned operand
fetches will not cause an address error exception.
Any attempted use of a word-sized index register (Xn.w) or an invalid scale factor on an
indexed effective addressing mode generates an address error. The setting of the extension
word valid (EV) bit on an indexed addressing mode instruction will also generate an address
error. Refer to the
ColdFire Programmer’s Reference Manual Rev. 1.0
(MCF5200PRM/AD).
4.2.4 Illegal Instruction Exception
The attempted execution of the $0000 and the $4AFC opwords generates an illegal
instruction exception, vector number $4. The ColdFire2/2M does not provide illegal
instruction detection on the extension words on any instruction, including MOVEC. If any
other non-supported opcode is executed, the resulting operation is undefined and the
ColdFire2/2M’s behavior is unpredictable.
4.2.5 Privilege Violation Exception
The attempted execution of a supervisor mode instruction while in user mode generates a
privilege violation exception, vector number $8. See the
Manual Rev. 1.0
for lists of supervisor- and user- mode instructions.
ColdFire Programmer’s Reference
4.2.6 Trace Exception
To aid in program development, the ColdFire2/2M provides an instruction-by-instruction
tracing capability. While in trace mode, indicated by the setting of the T-bit in the status
register (SR[15] = 1), the completion of an instruction execution triggers a trace exception,
vector number $9. This functionality allows a debugger to monitor program execution.
The single exception to this definition is the STOP instruction. A STOP instruction that
begins execution in trace mode (T-bit in SR set) or enters trace mode because of the STOP
instruction execution (bit 15 of the STOP operand is set) forces a trace exception after it
loads the SR. Upon return from the trace exception handler, execution continues with the
instruction following the STOP instruction, and the ColdFire2/2M never enters the stopped
condition. A STOP instruction will enter the stopped state only if the ColdFire2/2M is not in
trace mode before the STOP instruction is executed and the STOP instruction does not
place the ColdFire2/2M in the trace mode.
Since theColdFire2/2M does not support hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other
exception types. As an example, consider the execution of a TRAP instruction while in trace
mode. The ColdFire2/2M will initiate the TRAP exception and then pass control to the
corresponding exception handler, clearing the trace bit (T-bit) in the SR. If the system
requires that a trace exception be processed, it is the responsibility of the TRAP exception
handler to check for this condition, SR[15] in the exception stack frame, and pass control to
the trace exception handler before returning from the original exception.
F
Freescale Semiconductor, Inc.
n
.
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