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| 型號(hào)： | COLDFIRE3UM |
| 英文描述： | Version 3 ColdFire Core User＇s Manual |
| 中文描述： | 版本3 ColdFire內(nèi)核的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 144/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE3UM |
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Debug Support
MOTOROLA
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
7-7
There are two special cases involving the assertion of the BKPTB pin to be considered.
After the master reset signal (MRSTB) is negated, the processor waits for 16 clock cycles
before beginning reset exception processing. If the BKPTB input pin is asserted within the
first eight cycles after MRSTB is negated, the processor will enter the halt state, signaling
that halt status, $F, on the PST outputs. While in this state, all resources accessible via the
debug module can be referenced. This is the only opportunity to force the ColdFire2/2M into
emulation mode via the EMU bit in the configuration/status register (CSR). Once the system
initialization is complete, the processor response to a BDM GO command is dependent on
the set of BDM commands performed while breakpointed. Specifically, if the processor’s PC
register was loaded, then the GO command simply causes the processor to exit the halted
state and pass control to the instruction address contained in the PC. Note in this case, the
normal reset exception processing is bypassed. Conversely, if the PC register was not
loaded, then the GO command causes the processor to exit the halted state and continue
with reset exception processing.
The ColdFire2/2M also handles a special case with the assertion of BKPTB while the
processor is stopped by execution of the STOP instruction. For this case, the processor exits
the stopped mode and enters the halted state. Once halted, the standard BDM commands
may be exercised. When the processor is restarted, it continues with the execution of the
next sequential instruction, i.e., the instruction following the STOP opcode.
The halt source is indicated in CSR[27:24]; for simultaneous halt conditions, the highest
priority source is indicated.
7.3.2 BDM Serial Interface
Once the CPU is halted and the halt status reflected on the PST outputs (PST[3:0] = $F),
the development system may send unrestricted commands to the debug module. The
debug module implements a synchronous protocol using a three-pin interface: development
serial clock (DSCLK), development serial input (DSI), and development serial output (DSO).
The development system serves as the serial communication channel master and is
responsible for generation of the clock (DSCLK). The operating range of the serial channel
is DC to 1/2 of the processor frequency. The channel uses a full duplex mode, where data
is transmitted and received simultaneously by both master and slave devices. The
transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data
word. As seen in
Figure 7-3
, data is exchanged on the positive edge of CLK when DSCLK
is high (i.e. DSI is sampled and DSO is driven.) The DSCLK signal must also be sampled
low (on a positive edge of CLK) between each bit exchange. The MSB is transferred first.
F
Freescale Semiconductor, Inc.
n
.
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