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| 型號(hào)： | COLDFIRE3UM |
| 英文描述： | Version 3 ColdFire Core User＇s Manual |
| 中文描述： | 版本3 ColdFire內(nèi)核的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 143/253頁(yè) |
| 文件大?。?/td> | 1762K |
| 代理商： | COLDFIRE3UM |
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Debug Support
7-6
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
On CPU32 parts, the DSO signal can inform hardware that a serial transfer can start.
ColdFire clocking schemes restrict the use of this bit. Because DSO changes only when
DSCLK is high, DSO cannot be used to indicate the start of a serial transfer. The
development system should use either a free-running DSCLK or count the number of
clocks in any given transfer.
The read/write system register commands, RSREG and WSREG, have been replaced
by read/write control register commands, RCREG and WCREG. These commands use
the register coding scheme from the MOVEC instruction.
The read/write debug module register commands, RDMREG and WDMREG, have
been added to support debug module register accesses.
CALL and RST commands are not supported and will generate an illegal command
response.
Illegal command responses can be returned using the FILL and DUMP commands.
For any command performing a byte-sized memory read operation, the upper 8 bits of
the response data are undefined. The referenced data is returned in the lower 8 bits of
the response.
The debug module forces alignment for memory-referencing operations: long accesses
are forced to a 0-modulo-4 address; word accesses are forced to a 0-modulo-2
address. An address error response can no longer be returned.
7.3.1 CPU Halt
Although some BDM operations can occur in parallel with CPU operation, unrestricted BDM
operation requires the CPU to be halted. A number of sources can cause the CPU to halt,
including the following as shown in order of priority:
1. The occurrence of the catastrophic fault-on-fault condition automatically halts the
processor. The halt status, $F, is posted on the PST port.
2. The occurrence of a hardware breakpoint can be configured to generate a pending halt
condition in a manner similar to the assertion of the BKPTB signal. In all cases, the
occurrence of this type of breakpoint halts the processor in an imprecise manner.
Once the hardware breakpoint is asserted, the processor halts at the next sample
point. See
Section 7.4.1 Theory of Operation
3. The execution of the HALT
,
also known as BGND on the 683xx devices, instruction
immediately suspends execution and posts the halt status ($F) on the PST outputs.
By default, this is a supervisor instruction and attempted execution while in user mode
generates a privilege-violation exception. A User Halt Enable (UHE) control bit is
provided in the Configuration/Status Register (CSR) to allow execution of HALT in
user mode.
4. The assertion of the BKPTB input pin is treated as a pseudo-interrupt, i.e., the halt
condition is made pending until the processor core samples for halts/interrupts. The
processor samples for these conditions once during the execution of each instruction.
If there is a pending halt condition at the sample time, the processor suspends
execution and enters the halted state. The halt status, $F, is reflected in the PST
outputs.
for more detail.
F
Freescale Semiconductor, Inc.
n
.
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| COLINKEX | 制造商:Embest Info&Tech Co Ltd 功能描述:ADAPTER DEBUG SW/JTAG 制造商:EMBEST 功能描述:ADAPTER, DEBUG, SW/JTAG 制造商:EMBEST 功能描述:DEBUGGER, LPC13XX; Silicon Family Name:LPC13xx; Core Architecture:ARM; Core Sub-Architecture:Cortex-M3; IC Product Type:Debugger; Features:Support Cortex M0 and Cortex M3 Devices, Support Software & JTAG Debugging ;RoHS Compliant: Yes |
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