參數(shù)資料
型號(hào)： AD9925BBCZ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 80/96頁(yè)
文件大小： 1447K
代理商： AD9925BBCZ
AD9925
Table 66. Vertical Sequence 8 (VSEQ8) Register Map
Address Data Bit Content
C0
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
C1
[11:0]
[23:12]
C2
[11:0]
[23:12]
C3
[11:0]
[23:12]
C4
[11:0]
[23:12]
C5
[11:0]
[23:12]
C6
[11:0]
[23:12]
C7
[11:0]
[23:12]
Rev. A | Page 80 of 96
Default Value
X
X
X
X
X
X
X
Register Name
HBLKMASK_8
CLPOBPOL_8
PBLKPOL_8
VPATSEL_8
VMASK_8
HBLKALT_8
HDLEN13_8
UNUSED
VPATREPO_8
VPATREPE_8
VPATSTART_8
HDLEN_8
Register Description
Masking Polarity during HBLK. H1 [0], H3 [1].
CLPOB Start Polarity.
PBLK Start Polarity.
Selected Vertical Pattern Group for Vertical Sequence 8.
Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME
Registers).
Enable HBLK Alternation.
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixels.
Unused.
Number of Selected Vertical Pattern Group Repetitions for Odd Lines.
Number of Selected Vertical Pattern Group Repetitions for Even Lines.
Start Position in the Line for the Selected Vertical Pattern Group.
HD Line Length (Number of Pixels) for Vertical Sequence 8.
PBLK Toggle Position 1 for Vertical Sequence 8.
PBLK Toggle Position 2 for Vertical Sequence 8.
HBLK Toggle Position 1 for Vertical Sequence 8.
HBLK Toggle Position 2 for Vertical Sequence 8.
HBLK Toggle Position 3 for Vertical Sequence 8.
HBLK Toggle Position 4 for Vertical Sequence 8.
HBLK Toggle Position 5 for Vertical Sequence 8.
HBLK Toggle Position 6 for Vertical Sequence 8.
CLPOB Toggle Position 1 for Vertical Sequence 8.
CLPOB Toggle Position 2 for Vertical Sequence 8.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PBLKTOG1_8
PBLKTOG2_8
HBLKTOG1_8
HBLKTOG2_8
HBLKTOG3_8
HBLKTOG4_8
HBLKTOG5_8
HBLKTOG6_8
CLPOBTOG1_8
CLPOBTOG2_8
Table 67. Vertical Sequence 9 (VSEQ9) Register Map
Address Data Bit Content Default Value
C8
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[12]
[23:12]
C9
[11:0]
[23:12]
Register Name
HBLKMASK_9
CLPOBPOL_9
PBLKPOL_9
VPATSEL_9
VMASK_9
HBLKALT_9
HDLEN13_9
UNUSED
VPATREPO_9
VPATREPE_9
Register Description
Masking Polarity during HBLK. H1 [0], H3 [1].
CLPOB Start Polarity.
PBLK Start Polarity.
Selected Vertical Pattern Group for Vertical Sequence 9.
Enable Masking of Vertical Outputs (Specified by FREEZE/RESUME
registers).
Enable HBLK Alternation.
13
th
Bit for HD Length Counter Allows HD Length up to 8191 Pixels.
Unused.
Number of Selected Vertical Pattern Group Repetitions for Odd
Lines.
Number of Selected Vertical Pattern Group Repetitions for Even
Lines.
Start Position in the Line for the Selected Vertical Pattern Group.
HD Line Length (Number of Pixels) for Vertical Sequence 9.
PBLK Toggle Position 1 for Vertical Sequence 9.
PBLK Toggle Position 2 for Vertical Sequence 9.
HBLK Toggle Position 1 for Vertical Sequence 9.
HBLK Toggle Position 2 for Vertical Sequence 9.
HBLK Toggle Position 3 for Vertical Sequence 9.
HBLK Toggle Position 4 for Vertical Sequence 9.
HBLK Toggle Position 5 for Vertical Sequence 9.
HBLK Toggle Position 6 for Vertical Sequence 9.
CLPOB Toggle Position 1 for Vertical Sequence 9.
CLPOB Toggle Position 2 for Vertical Sequence 9.
X
X
X
X
X
X
X
X
X
CA
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
X
X
X
X
X
X
X
X
X
X
X
X
VPATSTART_9
HDLEN_9
PBLKTOG1_9
PBLKTOG2_9
HBLKTOG1_9
HBLKTOG2_9
HBLKTOG3_9
HBLKTOG4_9
HBLKTOG5_9
HBLKTOG6_9
CLPOBTOG1_9
CLPOBTOG2_9
CB
CC
CD
CE
CF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9925BBCZRL 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR
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AD9926BBCZRL 制造商:Analog Devices 功能描述:
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