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參數(shù)資料
| 型號(hào)： | AD9925BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 47/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZ |
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AD9925
VERTICAL DRIVER SIGNAL CONFIGURATION
As shown in Figure 57, XV1 to XV8, XSG1 to XSG6, and
XSUBCK are outputs from the internal AD9925 timing genera-
tor, while V1 to V8 and SUBCK are the resulting outputs from
the AD9925 vertical driver. The vertical driver performs the
mixing of the XV and XSG pulses and amplifies them to the
high voltages required for driving the CCD. Additionally, the
vertical driver outputs are inverted from the internal XV, XSG,
and SUBCK polarities configured by the AD9925 registers.
Rev. A | Page 47 of 96
Table 22 to Table 32 describe the output polarities for these
signals vs. their input levels. Refer to these tables when deter-
mining the register settings for the desired output levels.
Figure 58 to Figure 64 show graphically the relationship between
the polarities of the XV and XSG signals and the inverted verti-
cal driver output signals.
V3A
V5A
V4
V6
V7
V8
SUBCK
V2
V3B
V5B
V1
INTERNAL
TIMING
GENERATOR
XV1
XV4
XSG1
+3V
VERTICAL DRIVER
+15V,–7.5V
XV6
XV7
XV8
XSUBCK
XV2
XSG6
XV3
XSG2
XSG3
XSG4
XV5
XSG5
B8
G11
B9
C9
D9
E9
G10
H10
K10
J9
J8
AD9925
3-LEVEL OUTPUTS
2-LEVEL OUTPUTS
0
Figure 57. AD9925 Internal V-Driver Input Signals
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